component
SN74LS132DR
Public Made by Adomby adom
lingxingic Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SN74LS132DR
lingxingic · Logic Gates · SOP-14
SN74LS132DR from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of NAND gate 1, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 2 | 1B | input | Data input 1B of NAND gate 1, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 3 | 1Y | output | Data output 1Y of NAND gate 1, driven to the logic state given by the NAND truth table (Y is low only when both inputs are high). |
| 4 | 2A | input | Data input 2A of NAND gate 2, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 5 | 2B | input | Data input 2B of NAND gate 2, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 6 | 2Y | output | Data output 2Y of NAND gate 2, driven to the logic state given by the NAND truth table (Y is low only when both inputs are high). |
| 7 | GND | power_in | Ground (0 V) reference for the device; the datasheet specifies GND = 0 V for all test conditions. |
| 8 | 3Y | output | Data output 3Y of NAND gate 3, driven to the logic state given by the NAND truth table (Y is low only when both inputs are high). |
| 9 | 3A | input | Data input 3A of NAND gate 3, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 10 | 3B | input | Data input 3B of NAND gate 3, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 11 | 4Y | output | Data output 4Y of NAND gate 4, driven to the logic state given by the NAND truth table (Y is low only when both inputs are high). |
| 12 | 4A | input | Data input 4A of NAND gate 4, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 13 | 4B | input | Data input 4B of NAND gate 4, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 14 | VCC | power_in | Power supply voltage; recommended operating range is 2.0 V to 6.0 V (typical 5.0 V), with absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 8 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V or VI>VCC+0.5V | 8 | |
| Output clamp current | IOK | -20 | 20 | mA | VO<-0.5V or VO>VCC+0.5V | 8 | |
| Output current | IO | -25 | 25 | mA | -0.5V<VO<VCC+0.5V | 8 | |
| Supply current (absolute maximum) | ICC | 50 | mA | 8 | |||
| Ground current | IGND | -50 | mA | 8 | |||
| Total power dissipation | Ptot | 500 | mW | 8 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 8 | ||
| Soldering temperature | TL | 260 | ℃ | 10 s; SOP/TSSOP | 8 | ||
| Supply voltage (recommended) | VCC | 2 | 5 | 6 | V | 8 | |
| Input voltage (recommended) | VI | 0 | V | 8 | |||
| Output voltage (recommended) | VO | 0 | V | 8 | |||
| Operating ambient temperature | Tamb | -40 | 125 | ℃ | 8 | ||
| High-level output voltage (25℃) | VOH | 1.9 | 2 | V | Tamb=25℃; VI=VT+ or VT-; IO=-20uA; VCC=2.0V | 9 | |
| High-level output voltage (25℃) | VOH | 4.4 | 4.5 | V | Tamb=25℃; VI=VT+ or VT-; IO=-20uA; VCC=4.5V | 9 | |
| High-level output voltage (25℃) | VOH | 5.9 | 6 | V | Tamb=25℃; VI=VT+ or VT-; IO=-20uA; VCC=6.0V | 9 | |
| High-level output voltage (25℃) | VOH | 3.98 | 4.32 | V | Tamb=25℃; VI=VT+ or VT-; IO=-4.0mA; VCC=4.5V | 9 | |
| High-level output voltage (25℃) | VOH | 5.48 | 5.81 | V | Tamb=25℃; VI=VT+ or VT-; IO=-5.2mA; VCC=6.0V | 9 | |
| Low-level output voltage (25℃) | VOL | 0 | 0.1 | V | Tamb=25℃; VI=VT+ or VT-; IO=20uA; VCC=2.0V | 9 | |
| Low-level output voltage (25℃) | VOL | 0.15 | 0.26 | V | Tamb=25℃; VI=VT+ or VT-; IO=4.0mA; VCC=4.5V | 9 | |
| Low-level output voltage (25℃) | VOL | 0.16 | 0.26 | V | Tamb=25℃; VI=VT+ or VT-; IO=5.2mA; VCC=6.0V | 9 | |
| Input leakage current (25℃) | II | -1 | 1 | uA | Tamb=25℃; VI=VCC or GND; VCC=6.0V | 9 | |
| Static supply current (25℃) | ICC | 2 | uA | Tamb=25℃; VI=VCC or GND; IO=0A; VCC=6.0V | 9 | ||
| High-level output voltage (-40℃~+125℃) | VOH | 1.9 | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=-20uA; VCC=2.0V | 11 | ||
| High-level output voltage (-40℃~+125℃) | VOH | 4.4 | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=-20uA; VCC=4.5V | 11 | ||
| High-level output voltage (-40℃~+125℃) | VOH | 5.9 | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=-20uA; VCC=6.0V | 11 | ||
| High-level output voltage (-40℃~+125℃) | VOH | 3.7 | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=-4.0mA; VCC=4.5V | 11 | ||
| High-level output voltage (-40℃~+125℃) | VOH | 5.2 | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=-5.2mA; VCC=6.0V | 11 | ||
| Low-level output voltage (-40℃~+125℃) | VOL | 0.1 | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=20uA; VCC=2.0V | 11 | ||
| Low-level output voltage (-40℃~+125℃) | VOL | 0.4 | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=4.0mA; VCC=4.5V | 11 | ||
| Input leakage current (-40℃~+125℃) | II | -1 | 1 | uA | Tamb=-40℃~+125℃; VI=VCC or GND; VCC=6.0V | 11 | |
| Static supply current (-40℃~+125℃) | ICC | 40 | uA | Tamb=-40℃~+125℃; VI=VCC or GND; IO=0A; VCC=6.0V | 11 | ||
| Propagation delay nA, nB to nY (25℃) | tpd | 36 | 125 | ns | Tamb=25℃; 见图5; VCC=2.0V | 12 | |
| Propagation delay nA, nB to nY (25℃) | tpd | 13 | 25 | ns | Tamb=25℃; 见图5; VCC=4.5V | 12 | |
| Propagation delay nA, nB to nY (25℃) | tpd | 11 | ns | Tamb=25℃; 见图5; VCC=5.0V; CL=15pF | 12 | ||
| Propagation delay nA, nB to nY (25℃) | tpd | 10 | 21 | ns | Tamb=25℃; 见图5; VCC=6.0V | 12 | |
| Transition time (25℃) | tt | 19 | 75 | ns | Tamb=25℃; 见图5; VCC=2.0V | 12 | |
| Transition time (25℃) | tt | 7 | 15 | ns | Tamb=25℃; 见图5; VCC=4.5V | 12 | |
| Transition time (25℃) | tt | 6 | 13 | ns | Tamb=25℃; 见图5; VCC=6.0V | 12 | |
| Propagation delay nA, nB to nY (-40℃~+125℃) | tpd | 190 | ns | Tamb=-40℃~+125℃; 见图5; VCC=2.0V | 13 | ||
| Propagation delay nA, nB to nY (-40℃~+125℃) | tpd | 38 | ns | Tamb=-40℃~+125℃; 见图5; VCC=4.5V | 13 | ||
| Propagation delay nA, nB to nY (-40℃~+125℃) | tpd | 32 | ns | Tamb=-40℃~+125℃; 见图5; VCC=6.0V | 13 | ||
| Transition time (-40℃~+125℃) | tt | 110 | ns | Tamb=-40℃~+125℃; 见图5; VCC=2.0V | 13 | ||
| Transition time (-40℃~+125℃) | tt | 22 | ns | Tamb=-40℃~+125℃; 见图5; VCC=4.5V | 13 | ||
| Transition time (-40℃~+125℃) | tt | 19 | ns | Tamb=-40℃~+125℃; 见图5; VCC=6.0V | 13 | ||
| Positive-going threshold voltage VT+ (-40℃~+125℃) | VT+ | 0.7 | 1.5 | V | Tamb=-40℃~+125℃; VCC=2.0V | 15 | |
| Positive-going threshold voltage VT+ (-40℃~+125℃) | VT+ | 1.7 | 3.15 | V | Tamb=-40℃~+125℃; VCC=4.5V | 15 | |
| Positive-going threshold voltage VT+ (-40℃~+125℃) | VT+ | 2.1 | 4.2 | V | Tamb=-40℃~+125℃; VCC=6.0V | 15 | |
| Negative-going threshold voltage VT- (-40℃~+125℃) | VT- | 0.3 | 1 | V | Tamb=-40℃~+125℃; VCC=2.0V | 15 | |
| Negative-going threshold voltage VT- (-40℃~+125℃) | VT- | 0.9 | 2.2 | V | Tamb=-40℃~+125℃; VCC=4.5V | 15 | |
| Negative-going threshold voltage VT- (-40℃~+125℃) | VT- | 1.2 | 3 | V | Tamb=-40℃~+125℃; VCC=6.0V | 15 | |
| Hysteresis voltage VH (-40℃~+125℃) | VH | 0.2 | 1 | V | Tamb=-40℃~+125℃; VCC=2.0V | 15 | |
| Hysteresis voltage VH (-40℃~+125℃) | VH | 0.4 | 1.4 | V | Tamb=-40℃~+125℃; VCC=4.5V | 15 | |
| Hysteresis voltage VH (-40℃~+125℃) | VH | 0.6 | 1.6 | V | Tamb=-40℃~+125℃; VCC=6.0V | 15 |
CAD (KiCad official)
- Symbol:
SN74LS132DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ls132dr-etched.step/sn74ls132dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls132dr.step/sn74ls132dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (20 pp, sha256
5ba5bec7311eb3b3, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74LS132DR
**lingxingic** · Logic Gates · SOP-14
SN74LS132DR from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of NAND gate 1, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 2 | 1B | input | Data input 1B of NAND gate 1, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 3 | 1Y | output | Data output 1Y of NAND gate 1, driven to the logic state given by the NAND truth table (Y is low only when both inputs are high). |
| 4 | 2A | input | Data input 2A of NAND gate 2, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 5 | 2B | input | Data input 2B of NAND gate 2, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 6 | 2Y | output | Data output 2Y of NAND gate 2, driven to the logic state given by the NAND truth table (Y is low only when both inputs are high). |
| 7 | GND | power_in | Ground (0 V) reference for the device; the datasheet specifies GND = 0 V for all test conditions. |
| 8 | 3Y | output | Data output 3Y of NAND gate 3, driven to the logic state given by the NAND truth table (Y is low only when both inputs are high). |
| 9 | 3A | input | Data input 3A of NAND gate 3, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 10 | 3B | input | Data input 3B of NAND gate 3, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 11 | 4Y | output | Data output 4Y of NAND gate 4, driven to the logic state given by the NAND truth table (Y is low only when both inputs are high). |
| 12 | 4A | input | Data input 4A of NAND gate 4, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 13 | 4B | input | Data input 4B of NAND gate 4, a Schmitt-trigger input with input clamp diodes that allows current-limited connection to voltages above VCC. |
| 14 | VCC | power_in | Power supply voltage; recommended operating range is 2.0 V to 6.0 V (typical 5.0 V), with absolute maximum 7 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | | 7 | V | | 8 |
| Input clamp current | IIK | -20 | | 20 | mA | VI<-0.5V or VI>VCC+0.5V | 8 |
| Output clamp current | IOK | -20 | | 20 | mA | VO<-0.5V or VO>VCC+0.5V | 8 |
| Output current | IO | -25 | | 25 | mA | -0.5V<VO<VCC+0.5V | 8 |
| Supply current (absolute maximum) | ICC | | | 50 | mA | | 8 |
| Ground current | IGND | -50 | | | mA | | 8 |
| Total power dissipation | Ptot | | | 500 | mW | | 8 |
| Storage temperature | Tstg | -65 | | 150 | ℃ | | 8 |
| Soldering temperature | TL | | | 260 | ℃ | 10 s; SOP/TSSOP | 8 |
| Supply voltage (recommended) | VCC | 2 | 5 | 6 | V | | 8 |
| Input voltage (recommended) | VI | 0 | | | V | | 8 |
| Output voltage (recommended) | VO | 0 | | | V | | 8 |
| Operating ambient temperature | Tamb | -40 | | 125 | ℃ | | 8 |
| High-level output voltage (25℃) | VOH | 1.9 | 2 | | V | Tamb=25℃; VI=VT+ or VT-; IO=-20uA; VCC=2.0V | 9 |
| High-level output voltage (25℃) | VOH | 4.4 | 4.5 | | V | Tamb=25℃; VI=VT+ or VT-; IO=-20uA; VCC=4.5V | 9 |
| High-level output voltage (25℃) | VOH | 5.9 | 6 | | V | Tamb=25℃; VI=VT+ or VT-; IO=-20uA; VCC=6.0V | 9 |
| High-level output voltage (25℃) | VOH | 3.98 | 4.32 | | V | Tamb=25℃; VI=VT+ or VT-; IO=-4.0mA; VCC=4.5V | 9 |
| High-level output voltage (25℃) | VOH | 5.48 | 5.81 | | V | Tamb=25℃; VI=VT+ or VT-; IO=-5.2mA; VCC=6.0V | 9 |
| Low-level output voltage (25℃) | VOL | | 0 | 0.1 | V | Tamb=25℃; VI=VT+ or VT-; IO=20uA; VCC=2.0V | 9 |
| Low-level output voltage (25℃) | VOL | | 0.15 | 0.26 | V | Tamb=25℃; VI=VT+ or VT-; IO=4.0mA; VCC=4.5V | 9 |
| Low-level output voltage (25℃) | VOL | | 0.16 | 0.26 | V | Tamb=25℃; VI=VT+ or VT-; IO=5.2mA; VCC=6.0V | 9 |
| Input leakage current (25℃) | II | -1 | | 1 | uA | Tamb=25℃; VI=VCC or GND; VCC=6.0V | 9 |
| Static supply current (25℃) | ICC | | | 2 | uA | Tamb=25℃; VI=VCC or GND; IO=0A; VCC=6.0V | 9 |
| High-level output voltage (-40℃~+125℃) | VOH | 1.9 | | | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=-20uA; VCC=2.0V | 11 |
| High-level output voltage (-40℃~+125℃) | VOH | 4.4 | | | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=-20uA; VCC=4.5V | 11 |
| High-level output voltage (-40℃~+125℃) | VOH | 5.9 | | | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=-20uA; VCC=6.0V | 11 |
| High-level output voltage (-40℃~+125℃) | VOH | 3.7 | | | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=-4.0mA; VCC=4.5V | 11 |
| High-level output voltage (-40℃~+125℃) | VOH | 5.2 | | | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=-5.2mA; VCC=6.0V | 11 |
| Low-level output voltage (-40℃~+125℃) | VOL | | | 0.1 | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=20uA; VCC=2.0V | 11 |
| Low-level output voltage (-40℃~+125℃) | VOL | | | 0.4 | V | Tamb=-40℃~+125℃; VI=VT+ or VT-; IO=4.0mA; VCC=4.5V | 11 |
| Input leakage current (-40℃~+125℃) | II | -1 | | 1 | uA | Tamb=-40℃~+125℃; VI=VCC or GND; VCC=6.0V | 11 |
| Static supply current (-40℃~+125℃) | ICC | | | 40 | uA | Tamb=-40℃~+125℃; VI=VCC or GND; IO=0A; VCC=6.0V | 11 |
| Propagation delay nA, nB to nY (25℃) | tpd | | 36 | 125 | ns | Tamb=25℃; 见图5; VCC=2.0V | 12 |
| Propagation delay nA, nB to nY (25℃) | tpd | | 13 | 25 | ns | Tamb=25℃; 见图5; VCC=4.5V | 12 |
| Propagation delay nA, nB to nY (25℃) | tpd | | 11 | | ns | Tamb=25℃; 见图5; VCC=5.0V; CL=15pF | 12 |
| Propagation delay nA, nB to nY (25℃) | tpd | | 10 | 21 | ns | Tamb=25℃; 见图5; VCC=6.0V | 12 |
| Transition time (25℃) | tt | | 19 | 75 | ns | Tamb=25℃; 见图5; VCC=2.0V | 12 |
| Transition time (25℃) | tt | | 7 | 15 | ns | Tamb=25℃; 见图5; VCC=4.5V | 12 |
| Transition time (25℃) | tt | | 6 | 13 | ns | Tamb=25℃; 见图5; VCC=6.0V | 12 |
| Propagation delay nA, nB to nY (-40℃~+125℃) | tpd | | | 190 | ns | Tamb=-40℃~+125℃; 见图5; VCC=2.0V | 13 |
| Propagation delay nA, nB to nY (-40℃~+125℃) | tpd | | | 38 | ns | Tamb=-40℃~+125℃; 见图5; VCC=4.5V | 13 |
| Propagation delay nA, nB to nY (-40℃~+125℃) | tpd | | | 32 | ns | Tamb=-40℃~+125℃; 见图5; VCC=6.0V | 13 |
| Transition time (-40℃~+125℃) | tt | | | 110 | ns | Tamb=-40℃~+125℃; 见图5; VCC=2.0V | 13 |
| Transition time (-40℃~+125℃) | tt | | | 22 | ns | Tamb=-40℃~+125℃; 见图5; VCC=4.5V | 13 |
| Transition time (-40℃~+125℃) | tt | | | 19 | ns | Tamb=-40℃~+125℃; 见图5; VCC=6.0V | 13 |
| Positive-going threshold voltage VT+ (-40℃~+125℃) | VT+ | 0.7 | | 1.5 | V | Tamb=-40℃~+125℃; VCC=2.0V | 15 |
| Positive-going threshold voltage VT+ (-40℃~+125℃) | VT+ | 1.7 | | 3.15 | V | Tamb=-40℃~+125℃; VCC=4.5V | 15 |
| Positive-going threshold voltage VT+ (-40℃~+125℃) | VT+ | 2.1 | | 4.2 | V | Tamb=-40℃~+125℃; VCC=6.0V | 15 |
| Negative-going threshold voltage VT- (-40℃~+125℃) | VT- | 0.3 | | 1 | V | Tamb=-40℃~+125℃; VCC=2.0V | 15 |
| Negative-going threshold voltage VT- (-40℃~+125℃) | VT- | 0.9 | | 2.2 | V | Tamb=-40℃~+125℃; VCC=4.5V | 15 |
| Negative-going threshold voltage VT- (-40℃~+125℃) | VT- | 1.2 | | 3 | V | Tamb=-40℃~+125℃; VCC=6.0V | 15 |
| Hysteresis voltage VH (-40℃~+125℃) | VH | 0.2 | | 1 | V | Tamb=-40℃~+125℃; VCC=2.0V | 15 |
| Hysteresis voltage VH (-40℃~+125℃) | VH | 0.4 | | 1.4 | V | Tamb=-40℃~+125℃; VCC=4.5V | 15 |
| Hysteresis voltage VH (-40℃~+125℃) | VH | 0.6 | | 1.6 | V | Tamb=-40℃~+125℃; VCC=6.0V | 15 |
## CAD (KiCad official)
- Symbol: `SN74LS132DR`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74ls132dr-etched.step` / `sn74ls132dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ls132dr.step` / `sn74ls132dr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603367379691200512) (20 pp, sha256 `5ba5bec7311eb3b3`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74ls132dr-datasheet.pdf)