main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers sn74ls122n: viewers · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago
sn74ls122n-etched.glb Publish 0.1.0 · Ray 8d ago
sn74ls122n-etched.step sn74ls122n: factory component page (tier=mfr) · Ray 8d ago
sn74ls122n-hero.glb sn74ls122n: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
sn74ls122n-hero.overlay.json Publish 0.1.0 · Ray 8d ago
sn74ls122n.glb Publish 0.1.0 · Ray 8d ago
sn74ls122n.kicad_mod Publish 0.1.0 · Ray 8d ago
sn74ls122n.kicad_sym Publish 0.1.0 · Ray 8d ago
sn74ls122n.lbr Publish 0.1.0 · Ray 8d ago
sn74ls122n.step Publish 0.1.0 · Ray 8d ago

SN74LS122N

Texas Instruments · Monostable Multivibrators · PDIP-14

SN74LS122N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Active-low gated trigger input A1; a falling edge triggers the pulse when CLR is high and the other inputs are in their enabling states.
2 A2 input Active-low gated trigger input A2; a falling edge triggers the pulse when CLR is high and the other inputs are in their enabling states.
3 B1 input Active-high gated trigger input B1 with Schmitt hysteresis for jitter-free triggering at transition rates as slow as 0.1 mV per ns.
4 B2 input Active-high gated trigger input B2 with Schmitt hysteresis for jitter-free triggering at transition rates as slow as 0.1 mV per ns.
5 CLR input Active-low overriding clear input that terminates the output pulse.
6 Q̅ output Complementary (active-low) output of the monostable multivibrator.
7 GND power_in Ground.
8 Q output True (active-high) pulse output of the monostable multivibrator.
9 Rint passive Internal timing resistor (nominally 10 kΩ); connect to VCC to use it.
10 NC unconnected No internal connection.
11 Cext passive External timing capacitor connection; the capacitor goes between Cext and Rext/Cext (positive).
12 NC unconnected No internal connection.
13 Rext/Cext passive External timing resistor and capacitor connection (capacitor positive side); an external resistor goes to VCC with Rint open-circuited.
14 VCC power_in Positive supply voltage.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Logic ICs
Pins 14

CAD (KiCad official)

  • Symbol: SN74LS122N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74ls122n-etched.step / sn74ls122n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls122n.step / sn74ls122n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 3b63fa652f19f07e, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF