component
SN74LS11DR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 5d ago |
| viewers | 5d ago |
| package.json | 5d ago |
| page.json | 5d ago |
| README.md | 5d ago |
| sn74ls11dr-etched.glb | 5d ago |
| sn74ls11dr-etched.step | 5d ago |
| sn74ls11dr-hero.glb | 5d ago |
| sn74ls11dr-hero.overlay.json | 5d ago |
| sn74ls11dr.glb | 5d ago |
| sn74ls11dr.kicad_mod | 5d ago |
| sn74ls11dr.kicad_sym | 5d ago |
| sn74ls11dr.lbr | 5d ago |
| sn74ls11dr.step | 5d ago |
SN74LS11DR
Texas Instruments · Logic Gates · SOIC-14
SN74LS11DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A (AND input; output 1Y is high only when 1A, 1B and 1C are all high). |
| 2 | 1B | input | Gate 1 input B. |
| 3 | 2A | input | Gate 2 input A (AND input; output 2Y is high only when 2A, 2B and 2C are all high). |
| 4 | 2B | input | Gate 2 input B. |
| 5 | 2C | input | Gate 2 input C. |
| 6 | 2Y | output | Gate 2 output, Y = 2A·2B·2C. |
| 7 | GND | power_in | Ground; supply voltage values are specified with respect to this network ground terminal. |
| 8 | 3Y | output | Gate 3 output, Y = 3A·3B·3C. |
| 9 | 3A | input | Gate 3 input A (AND input; output 3Y is high only when 3A, 3B and 3C are all high). |
| 10 | 3B | input | Gate 3 input B. |
| 11 | 3C | input | Gate 3 input C. |
| 12 | 1Y | output | Gate 1 output, Y = 1A·1B·1C. |
| 13 | 1C | input | Gate 1 input C. |
| 14 | VCC | power_in | Positive supply; absolute maximum 7 V with respect to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature | 0 | 70 | °C | Op temp for SN74LS11DR (SOIC, 14 pins) in package option addendum | 5 |
CAD (KiCad official)
- Symbol:
SN74LS11DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ls11dr-etched.step/sn74ls11dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls11dr.step/sn74ls11dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
656505ea7f65b3ca, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).