component
SN74LS112AD
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74LS112AD
Texas Instruments · Flip Flops · SOIC-16
SN74LS112AD from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLK | input | Clock input of flip-flop 1, which transfers J/K data to the outputs on the negative-going edge. |
| 2 | 1K | input | K data input of flip-flop 1. |
| 3 | 1J | input | J data input of flip-flop 1. |
| 4 | 1PRE | input | Active-low asynchronous preset of flip-flop 1, which sets 1Q high regardless of the other inputs. |
| 5 | 1Q | output | True output of flip-flop 1. |
| 6 | 1Q̅ | output | Complementary output of flip-flop 1. |
| 7 | 2Q̅ | output | Complementary output of flip-flop 2. |
| 8 | GND | power_in | Ground; the reference for all voltage values. |
| 9 | 2Q | output | True output of flip-flop 2. |
| 10 | 2PRE | input | Active-low asynchronous preset of flip-flop 2, which sets 2Q high regardless of the other inputs. |
| 11 | 2J | input | J data input of flip-flop 2. |
| 12 | 2K | input | K data input of flip-flop 2. |
| 13 | 2CLK | input | Clock input of flip-flop 2, which transfers J/K data to the outputs on the negative-going edge. |
| 14 | 2CLR | input | Active-low asynchronous clear of flip-flop 2, which resets 2Q low regardless of the other inputs. |
| 15 | 1CLR | input | Active-low asynchronous clear of flip-flop 1, which resets 1Q low regardless of the other inputs. |
| 16 | VCC | power_in | Supply voltage; absolute maximum 7 V with respect to ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic ICs |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74LS112AD - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
sn74ls112ad-etched.step/sn74ls112ad-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls112ad.step/sn74ls112ad.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
7a8c138ea24b0780, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74LS112AD
**Texas Instruments** · Flip Flops · SOIC-16
SN74LS112AD from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLK | input | Clock input of flip-flop 1, which transfers J/K data to the outputs on the negative-going edge. |
| 2 | 1K | input | K data input of flip-flop 1. |
| 3 | 1J | input | J data input of flip-flop 1. |
| 4 | 1PRE | input | Active-low asynchronous preset of flip-flop 1, which sets 1Q high regardless of the other inputs. |
| 5 | 1Q | output | True output of flip-flop 1. |
| 6 | 1Q̅ | output | Complementary output of flip-flop 1. |
| 7 | 2Q̅ | output | Complementary output of flip-flop 2. |
| 8 | GND | power_in | Ground; the reference for all voltage values. |
| 9 | 2Q | output | True output of flip-flop 2. |
| 10 | 2PRE | input | Active-low asynchronous preset of flip-flop 2, which sets 2Q high regardless of the other inputs. |
| 11 | 2J | input | J data input of flip-flop 2. |
| 12 | 2K | input | K data input of flip-flop 2. |
| 13 | 2CLK | input | Clock input of flip-flop 2, which transfers J/K data to the outputs on the negative-going edge. |
| 14 | 2CLR | input | Active-low asynchronous clear of flip-flop 2, which resets 2Q low regardless of the other inputs. |
| 15 | 1CLR | input | Active-low asynchronous clear of flip-flop 1, which resets 1Q low regardless of the other inputs. |
| 16 | VCC | power_in | Supply voltage; absolute maximum 7 V with respect to ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic ICs |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `SN74LS112AD`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `sn74ls112ad-etched.step` / `sn74ls112ad-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ls112ad.step` / `sn74ls112ad.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](docs/sn74ls112ad-datasheet.pdf) (23 pp, sha256 `7a8c138ea24b0780`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74ls112ad-datasheet.pdf)