component
SN74LS10N
Public Made by Adomby adom
XBLW Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LS10N
XBLW · Logic Gates · DIP-14
SN74LS10N from XBLW, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input A of NAND gate 1 (1Y = NOT(1A AND 1B AND 1C)); inputs include clamp diodes, so current-limiting resistors can be used to interface inputs to voltages above VCC. |
| 2 | 1B | input | Data input B of NAND gate 1 (1Y = NOT(1A AND 1B AND 1C)); inputs include clamp diodes, so current-limiting resistors can be used to interface inputs to voltages above VCC. |
| 3 | 2A | input | Data input A of NAND gate 2 (2Y = NOT(2A AND 2B AND 2C)); inputs include clamp diodes, so current-limiting resistors can be used to interface inputs to voltages above VCC. |
| 4 | 2B | input | Data input B of NAND gate 2 (2Y = NOT(2A AND 2B AND 2C)); inputs include clamp diodes, so current-limiting resistors can be used to interface inputs to voltages above VCC. |
| 5 | 2C | input | Data input C of NAND gate 2 (2Y = NOT(2A AND 2B AND 2C)); inputs include clamp diodes, so current-limiting resistors can be used to interface inputs to voltages above VCC. |
| 6 | 2Y | output | Data output of NAND gate 2, low when all of 2A, 2B and 2C are high. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages in the datasheet. |
| 8 | 3Y | output | Data output of NAND gate 3, low when all of 3A, 3B and 3C are high. |
| 9 | 3A | input | Data input A of NAND gate 3 (3Y = NOT(3A AND 3B AND 3C)); inputs include clamp diodes, so current-limiting resistors can be used to interface inputs to voltages above VCC. |
| 10 | 3B | input | Data input B of NAND gate 3 (3Y = NOT(3A AND 3B AND 3C)); inputs include clamp diodes, so current-limiting resistors can be used to interface inputs to voltages above VCC. |
| 11 | 3C | input | Data input C of NAND gate 3 (3Y = NOT(3A AND 3B AND 3C)); inputs include clamp diodes, so current-limiting resistors can be used to interface inputs to voltages above VCC. |
| 12 | 1Y | output | Data output of NAND gate 1, low when all of 1A, 1B and 1C are high. |
| 13 | 1C | input | Data input C of NAND gate 1 (1Y = NOT(1A AND 1B AND 1C)); inputs include clamp diodes, so current-limiting resistors can be used to interface inputs to voltages above VCC. |
| 14 | VCC | power_in | Supply voltage; recommended operating range is 2.0 V to 6.0 V (typ. 5.0 V), absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XBLW |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74LS10N - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ls10n-etched.step/sn74ls10n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls10n.step/sn74ls10n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XBLW datasheet (13 pp, sha256
62325eef77def494, retrieved 2026-10-13, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).