component

SN74LS107N

Public Made by Adom

by adom

lingxingic Flip Flops, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74ls107nfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers sn74ls107n: viewers · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
sn74ls107n-etched.glb Publish 0.1.0 · Ray 5d ago
sn74ls107n-etched.step sn74ls107n: factory component page (tier=lcsc) · Ray 5d ago
sn74ls107n-hero.glb sn74ls107n: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
sn74ls107n-hero.overlay.json Publish 0.1.0 · Ray 5d ago
sn74ls107n.glb Publish 0.1.0 · Ray 5d ago
sn74ls107n.kicad_mod Publish 0.1.0 · Ray 5d ago
sn74ls107n.kicad_sym Publish 0.1.0 · Ray 5d ago
sn74ls107n.lbr Publish 0.1.0 · Ray 5d ago
sn74ls107n.step Publish 0.1.0 · Ray 5d ago

SN74LS107N

lingxingic · Flip Flops · DIP-14

SN74LS107N from lingxingic, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1J input Synchronous J input of flip-flop 1.
2 ~{1Q} output Complement output of flip-flop 1.
3 1Q output True output of flip-flop 1.
4 1K input Synchronous K input of flip-flop 1.
5 2Q output True output of flip-flop 2.
6 ~{2Q} output Complement output of flip-flop 2.
7 GND power_in Ground (0 V).
8 2J input Synchronous J input of flip-flop 2.
9 2CP input Clock input of flip-flop 2, triggered on the HIGH-to-LOW edge.
10 2R input Asynchronous reset input of flip-flop 2, active LOW.
11 2K input Synchronous K input of flip-flop 2.
12 1CP input Clock input of flip-flop 1, triggered on the HIGH-to-LOW edge.
13 1R input Asynchronous reset input of flip-flop 1, active LOW.
14 VCC power_in Supply voltage, recommended 2.0 V to 6.0 V (absolute maximum 7 V).

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 6
Supply current ICC 50 mA 6
Ground current IGND -50 mA 6
Input clamping current IIK -20 20 mA VI < -0.5V or VI > VCC+0.5V 6
Output clamping current IOK -20 20 mA VO < -0.5V or VO > VCC+0.5V 6
Output current IO -25 25 mA -0.5V < VO < VCC+0.5V 6
Storage temperature Tstg -65 150 °C 6
Soldering temperature TL 245 °C 10s, DIP 6
Supply voltage VCC 2 5 6 V 6
Input voltage VI 0 V max = VCC 6
Output voltage VO 0 V max = VCC 6
Ambient temperature Tamb -40 125 °C 6
HIGH-level input voltage VIH 1.5 1.2 V VCC=2.0V, Tamb=-40 to +85°C 7
HIGH-level input voltage VIH 3.15 2.4 V VCC=4.5V, Tamb=-40 to +85°C 7
HIGH-level input voltage VIH 4.2 3.2 V VCC=6.0V, Tamb=-40 to +85°C 7
LOW-level input voltage VIL 0.8 0.5 V VCC=2.0V, Tamb=-40 to +85°C 7
LOW-level input voltage VIL 2.1 1.35 V VCC=4.5V, Tamb=-40 to +85°C 7
LOW-level input voltage VIL 2.8 1.8 V VCC=6.0V, Tamb=-40 to +85°C 7
HIGH-level output voltage VOH 1.9 2 V VCC=2.0V, IO=-20uA, Tamb=-40 to +85°C 7
HIGH-level output voltage VOH 4.4 4.5 V VCC=4.5V, IO=-20uA, Tamb=-40 to +85°C 7
HIGH-level output voltage VOH 5.9 6 V VCC=6.0V, IO=-20uA, Tamb=-40 to +85°C 7
HIGH-level output voltage VOH 3.84 4.32 V VCC=4.5V, IO=-4.0mA, Tamb=-40 to +85°C 7
HIGH-level output voltage VOH 5.34 5.81 V VCC=6.0V, IO=-5.2mA, Tamb=-40 to +85°C 7
LOW-level output voltage VOL 0 0.1 V VCC=2.0V, IO=20uA, Tamb=-40 to +85°C 7
LOW-level output voltage VOL 0.15 0.33 V VCC=4.5V, IO=4.0mA, Tamb=-40 to +85°C 7
LOW-level output voltage VOL 0.16 0.33 V VCC=6.0V, IO=5.2mA, Tamb=-40 to +85°C 7
Input leakage current II -1 1 uA VCC=6.0V, VI=VCC or GND, Tamb=-40 to +85°C 7
Supply current ICC 80 uA VCC=6.0V, VI=VCC or GND; IO=0A, Tamb=-40 to +85°C 7
HIGH-level input voltage VIH 3.15 V VCC=4.5V, Tamb=-40 to +125°C 8
LOW-level input voltage VIL 1.35 V VCC=4.5V, Tamb=-40 to +125°C 8
HIGH-level output voltage VOH 3.7 V VCC=4.5V, IO=-4.0mA, Tamb=-40 to +125°C 8
HIGH-level output voltage VOH 5.2 V VCC=6.0V, IO=-5.2mA, Tamb=-40 to +125°C 8
LOW-level output voltage VOL 0.4 V VCC=4.5V, IO=4.0mA, Tamb=-40 to +125°C 8
Input leakage current II -1 1 uA VCC=6.0V, VI=VCC or GND, Tamb=-40 to +125°C 8
Supply current ICC 160 uA VCC=6.0V, VI=VCC or GND; IO=0A, Tamb=-40 to +125°C 8
nCP to nQ propagation delay tPLH, tPHL 19 32 ns VCC=4.5V, CL=50pF, Tamb=-40 to +85°C 9
nCP to nQ (complement) propagation delay tPLH, tPHL 19 40 ns VCC=4.5V, CL=50pF, Tamb=-40 to +85°C 9
nR to nQ/nQ propagation delay tPLH, tPHL 19 39 ns VCC=4.5V, CL=50pF, Tamb=-40 to +85°C 9
Output transition time tTHL, tTLH 7 19 ns VCC=4.5V, CL=50pF, Tamb=-40 to +85°C 9
nCP input HIGH or LOW pulse width tw 20 8 ns VCC=4.5V, CL=50pF, Tamb=-40 to +85°C 9
nR input HIGH pulse width tw 20 8 ns VCC=4.5V, CL=50pF, Tamb=-40 to +85°C 9
nR to nCP recovery time trec 15 7 ns VCC=4.5V, CL=50pF, Tamb=-40 to +85°C 9
nJ, nK to nCP set-up time tsu 25 8 ns VCC=4.5V, CL=50pF, Tamb=-40 to +85°C 9
nJ, nK to nCP hold time th 3 -2 ns VCC=4.5V, CL=50pF, Tamb=-40 to +85°C 9
Maximum clock frequency fmax 24 91 MHz VCC=4.5V, CL=50pF, Tamb=-40 to +85°C 9
nCP to nQ propagation delay tPLH, tPHL 48 ns VCC=4.5V, CL=50pF, Tamb=-40 to +125°C 10
nCP to nQ (complement) propagation delay tPLH, tPHL 48 ns VCC=4.5V, CL=50pF, Tamb=-40 to +125°C 10
nR to nQ/nQ propagation delay tPLH, tPHL 47 ns VCC=4.5V, CL=50pF, Tamb=-40 to +125°C 10
Output transition time tTHL, tTLH 22 ns VCC=4.5V, CL=50pF, Tamb=-40 to +125°C 10
nCP input HIGH or LOW pulse width tw 24 ns VCC=4.5V, CL=50pF, Tamb=-40 to +125°C 10
nR input HIGH pulse width tw 24 ns VCC=4.5V, CL=50pF, Tamb=-40 to +125°C 10
nR to nCP recovery time trec 18 ns VCC=4.5V, CL=50pF, Tamb=-40 to +125°C 10
nJ, nK to nCP set-up time tsu 30 ns VCC=4.5V, CL=50pF, Tamb=-40 to +125°C 10
nJ, nK to nCP hold time th 3 ns VCC=4.5V, CL=50pF, Tamb=-40 to +125°C 10
Maximum clock frequency fmax 20 MHz VCC=4.5V, CL=50pF, Tamb=-40 to +125°C 10

CAD (KiCad official)

  • Symbol: SN74LS107N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74ls107n-etched.step / sn74ls107n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls107n.step / sn74ls107n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (17 pp, sha256 1d0f95b594e5add7, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF