component
SN74LS107AN
Public Made by Adomby adom
Texas Instruments Flip Flops, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 10h ago |
| viewers | 10h ago |
| package.json | 10h ago |
| page.json | 10h ago |
| README.md | 10h ago |
| sn74ls107an-etched.glb | 10h ago |
| sn74ls107an-etched.step | 10h ago |
| sn74ls107an-hero.glb | 10h ago |
| sn74ls107an-hero.overlay.json | 10h ago |
| sn74ls107an.glb | 10h ago |
| sn74ls107an.kicad_mod | 10h ago |
| sn74ls107an.kicad_sym | 10h ago |
| sn74ls107an.lbr | 10h ago |
| sn74ls107an.step | 10h ago |
SN74LS107AN
Texas Instruments · Flip Flops · PDIP-14
SN74LS107AN from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1J | input | J data input of flip-flop 1; must be stable prior to the high-to-low clock transition. |
| 2 | 1Q̅ | output | Complementary (inverted) output of flip-flop 1, driven high when clear is low. |
| 3 | 1Q | output | True output of flip-flop 1, forced low when clear is low. |
| 4 | 1K | input | K data input of flip-flop 1; must be stable prior to the high-to-low clock transition. |
| 5 | 2Q | output | True output of flip-flop 2, forced low when clear is low. |
| 6 | 2Q̅ | output | Complementary (inverted) output of flip-flop 2, driven high when clear is low. |
| 7 | GND | power_in | Ground pin. |
| 8 | 2J | input | J data input of flip-flop 2; must be stable prior to the high-to-low clock transition. |
| 9 | 2CLK | input | Clock input of flip-flop 2, negative-edge triggered (high-to-low transition). |
| 10 | 2CLR̅ | input | Active-low direct clear of flip-flop 2; when low it overrides clock and data inputs, forcing Q low and Q̅ high. |
| 11 | 2K | input | K data input of flip-flop 2; must be stable prior to the high-to-low clock transition. |
| 12 | 1CLK | input | Clock input of flip-flop 1, negative-edge triggered (high-to-low transition). |
| 13 | 1CLR̅ | input | Active-low direct clear of flip-flop 1; when low it overrides clock and data inputs, forcing Q low and Q̅ high. |
| 14 | VCC | power_in | Positive supply voltage pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating free-air temperature range (orderable device, PDIP N package) | 0 | 70 | °C | SN74LS107AN, package option addendum Op Temp column | 6 |
CAD (KiCad official)
- Symbol:
SN74LS107AN - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ls107an-etched.step/sn74ls107an-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls107an.step/sn74ls107an.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (18 pp, sha256
bdc52a4e5d5dd402, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).