component
SN74LS04N
Public Made by Adomby adom
XBLW Inverters, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 8d ago |
| viewers | 8d ago |
| package.json | 8d ago |
| page.json | 8d ago |
| README.md | 8d ago |
| sn74ls04n-etched.glb | 8d ago |
| sn74ls04n-etched.step | 8d ago |
| sn74ls04n-hero.glb | 8d ago |
| sn74ls04n-hero.overlay.json | 8d ago |
| sn74ls04n.glb | 8d ago |
| sn74ls04n.kicad_mod | 8d ago |
| sn74ls04n.kicad_sym | 8d ago |
| sn74ls04n.lbr | 8d ago |
| sn74ls04n.step | 8d ago |
SN74LS04N
XBLW · Inverters · DIP-14
SN74LS04N from XBLW, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of inverter gate 1; the output 1Y is the logical inverse of this input (H gives L, L gives H). |
| 2 | 1Y | output | Data output of inverter gate 1, the inverse of 1A per the function table. |
| 3 | 2A | input | Data input of inverter gate 2; the output 2Y is the logical inverse of this input. |
| 4 | 2Y | output | Data output of inverter gate 2, the inverse of 2A per the function table. |
| 5 | 3A | input | Data input of inverter gate 3; the output 3Y is the logical inverse of this input. |
| 6 | 3Y | output | Data output of inverter gate 3, the inverse of 3A per the function table. |
| 7 | GND | power_in | Ground (0 V) reference for the device; all voltages are referenced to GND. |
| 8 | 4Y | output | Data output of inverter gate 4, the inverse of 4A per the function table. |
| 9 | 4A | input | Data input of inverter gate 4; the output 4Y is the logical inverse of this input. |
| 10 | 5Y | output | Data output of inverter gate 5, the inverse of 5A per the function table. |
| 11 | 5A | input | Data input of inverter gate 5; the output 5Y is the logical inverse of this input. |
| 12 | 6Y | output | Data output of inverter gate 6, the inverse of 6A per the function table. |
| 13 | 6A | input | Data input of inverter gate 6; the output 6Y is the logical inverse of this input. |
| 14 | VCC | power_in | Supply voltage; recommended operating range is 2.0 V to 6.0 V (absolute maximum 7 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XBLW |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 5 | ||
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 5 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 5 | |
| Output current | IO | -25 | 25 | mA | -0.5V < VO < VCC+0.5V | 5 | |
| Supply current | ICC | 50 | mA | 5 | |||
| Ground current | IGND | -50 | mA | 5 | |||
| Total power dissipation | Ptot | 500 | mW | 5 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 5 | ||
| Soldering temperature | TL | 260 | ℃ | 10 s, DIP package | 5 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 5 | |
| Input voltage | VI | 0 | V | 5 | |||
| Output voltage | VO | 0 | V | 5 | |||
| Input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 5 | ||
| Input transition rise and fall rate | Δt/ΔV | 139 | ns/V | VCC=4.5V | 5 | ||
| Input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 5 | ||
| Ambient temperature | Tamb | -20 | 85 | ℃ | 5 | ||
| HIGH-level input voltage | VIH | 3.15 | V | Tamb=25℃; VCC=4.5V | 6 | ||
| HIGH-level input voltage | VIH | 4.2 | V | Tamb=25℃; VCC=6.0V | 6 | ||
| LOW-level input voltage | VIL | 1.35 | V | Tamb=25℃; VCC=4.5V | 6 | ||
| LOW-level input voltage | VIL | 1.8 | V | Tamb=25℃; VCC=6.0V | 6 | ||
| HIGH-level output voltage | VOH | 1.9 | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V | 6 | ||
| HIGH-level output voltage | VOH | 4.4 | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V | 6 | ||
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | Tamb=25℃; VI=VIH or VIL; IO=-4.0mA; VCC=4.5V | 6 | |
| HIGH-level output voltage | VOH | 5.48 | 5.81 | V | Tamb=25℃; VI=VIH or VIL; IO=-5.2mA; VCC=6.0V | 6 | |
| LOW-level output voltage | VOL | 0.1 | V | Tamb=25℃; VI=VIH or VIL; IO=20uA; VCC=2.0V | 6 | ||
| LOW-level output voltage | VOL | 0.26 | V | Tamb=25℃; VI=VIH or VIL; IO=4.0mA; VCC=4.5V | 6 | ||
| Input leakage current | II | -1 | 1 | uA | Tamb=25℃; VI=VCC or GND; VCC=6.0V | 6 | |
| Supply current | ICC | 2 | uA | Tamb=25℃; VI=VCC or GND; IO=0A; VCC=6.0V | 6 | ||
| HIGH-level output voltage | VOH | 3.84 | V | Tamb=-20℃ to +85℃; VI=VIH or VIL; IO=-4.0mA; VCC=4.5V | 6 | ||
| HIGH-level output voltage | VOH | 5.34 | V | Tamb=-20℃ to +85℃; VI=VIH or VIL; IO=-5.2mA; VCC=6.0V | 6 | ||
| LOW-level output voltage | VOL | 0.33 | V | Tamb=-20℃ to +85℃; VI=VIH or VIL; IO=4.0mA; VCC=4.5V | 6 | ||
| Supply current | ICC | 20 | uA | Tamb=-20℃ to +85℃; VI=VCC or GND; IO=0A; VCC=6.0V | 6 | ||
| Propagation delay nA, nB to nY | tpd | 25 | 85 | ns | Tamb=25℃; VCC=2.0V; see Figure 5 | 7 | |
| Propagation delay nA, nB to nY | tpd | 9 | 17 | ns | Tamb=25℃; VCC=4.5V; see Figure 5 | 7 | |
| Transition time | tt | 75 | ns | Tamb=25℃; VCC=2.0V; see Figure 5 | 7 | ||
| Transition time | tt | 15 | ns | Tamb=25℃; VCC=4.5V; see Figure 5 | 7 | ||
| Transition time | tt | 13 | ns | Tamb=25℃; VCC=6.0V; see Figure 5 | 7 | ||
| Propagation delay nA, nB to nY | tpd | 105 | ns | Tamb=-20℃ to +85℃; VCC=2.0V; see Figure 5 | 7 | ||
| Propagation delay nA, nB to nY | tpd | 21 | ns | Tamb=-20℃ to +85℃; VCC=4.5V; see Figure 5 | 7 | ||
| Propagation delay nA, nB to nY | tpd | 18 | ns | Tamb=-20℃ to +85℃; VCC=6.0V; see Figure 5 | 7 | ||
| Transition time | tt | 95 | ns | Tamb=-20℃ to +85℃; VCC=2.0V; see Figure 5 | 7 | ||
| Transition time | tt | 19 | ns | Tamb=-20℃ to +85℃; VCC=4.5V; see Figure 5 | 7 | ||
| Transition time | tt | 16 | ns | Tamb=-20℃ to +85℃; VCC=6.0V; see Figure 5 | 7 |
CAD (KiCad official)
- Symbol:
SN74LS04N - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ls04n-etched.step/sn74ls04n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls04n.step/sn74ls04n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XBLW datasheet (13 pp, sha256
6d074ccbd2dc7713, retrieved 2026-10-14, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).