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SN74LS00NSR

Public Made by Adom

by adom

Texas Instruments Logic Gates, SOP-14-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs sn74ls00nsr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
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package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Initial commit: component/sn74ls00nsr · Ray 4d ago
sn74ls00nsr-etched.fit.json sn74ls00nsr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
sn74ls00nsr-etched.glb sn74ls00nsr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
sn74ls00nsr-etched.step sn74ls00nsr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
sn74ls00nsr.glb Publish 0.1.0 · Ray 4d ago
sn74ls00nsr.kicad_mod Publish 0.1.0 · Ray 4d ago
sn74ls00nsr.kicad_sym Publish 0.1.0 · Ray 4d ago
sn74ls00nsr.lbr Publish 0.1.0 · Ray 4d ago
sn74ls00nsr.step Publish 0.1.0 · Ray 4d ago

SN74LS00NSR

Texas Instruments · Logic Gates · SOP-14-208mil

SN74LS00NSR from Texas Instruments, in a SOP-14-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)
2 1B input Gate 1 input B; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)
3 1Y output Gate 1 output; NAND output Y = 1A·1B (IOL 8mA per operating conditions)
4 2A input Gate 2 input A; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)
5 2B input Gate 2 input B; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)
6 2Y output Gate 2 output; NAND output Y = 2A·2B (IOL 8mA per operating conditions)
7 GND power_in Ground reference; negative power supply connection
8 3Y output Gate 3 output; NAND output Y = 3A·3B (IOL 8mA per operating conditions)
9 3B input Gate 3 input B; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)
10 3A input Gate 3 input A; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)
11 4Y output Gate 4 output; NAND output Y = 4A·4B (IOL 8mA per operating conditions)
12 4B input Gate 4 input B; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)
13 4A input Gate 4 input A; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)
14 VCC power_in Positive power supply; operating range 4.75V to 5.25V for SN74LS00

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOP-14-208mil
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74LS00NSR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74ls00nsr-etched.step / sn74ls00nsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls00nsr.step / sn74ls00nsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 ac4bbf6801413a20, retrieved 2026-10-01, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF