component
SN74LS00NSR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOP-14-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
sn74ls00nsr: factory component page (tier=lcsc)
3 files changed
+17744−35
page.json+56−35@@ -1,8 +1,11 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74ls00nsr",+ "title": "SN74LS00NSR",+ "brief": "Texas Instruments Logic Gates, SOP-14-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Texas Instruments Logic Gates, SOP-14-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic",@@ -10,24 +13,6 @@ "factory-2.0.0", "extractor-text" ],- "dependencies": {},- "hero": {- "type": "image",- "path": "docs/hero.png"- },- "files": [- "page.json",- "README.md",- "sn74ls00nsr.kicad_sym",- "sn74ls00nsr.kicad_mod",- "sn74ls00nsr.glb",- "sn74ls00nsr.step",- "sn74ls00nsr.lbr",- "docs/hero.png",- "docs/sn74ls00nsr-datasheet.pdf",- "viewers/symbol.html",- "viewers/footprint.html"- ], "component": { "mpn": "SN74LS00NSR", "manufacturer": "Texas Instruments",@@ -68,37 +53,37 @@ "number": "1", "name": "1A", "type": "input",- "description": "Gate 1 input A; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)"+ "description": "Gate 1 input A; TTL-compatible 2-input NAND input (VIH \u2265 2V, VIL \u2264 0.8V)" }, { "number": "2", "name": "1B", "type": "input",- "description": "Gate 1 input B; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)"+ "description": "Gate 1 input B; TTL-compatible 2-input NAND input (VIH \u2265 2V, VIL \u2264 0.8V)" }, { "number": "3", "name": "1Y", "type": "output",- "description": "Gate 1 output; NAND output Y = 1A·1B (IOL 8mA per operating conditions)"+ "description": "Gate 1 output; NAND output Y = 1A\u00b71B (IOL 8mA per operating conditions)" }, { "number": "4", "name": "2A", "type": "input",- "description": "Gate 2 input A; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)"+ "description": "Gate 2 input A; TTL-compatible 2-input NAND input (VIH \u2265 2V, VIL \u2264 0.8V)" }, { "number": "5", "name": "2B", "type": "input",- "description": "Gate 2 input B; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)"+ "description": "Gate 2 input B; TTL-compatible 2-input NAND input (VIH \u2265 2V, VIL \u2264 0.8V)" }, { "number": "6", "name": "2Y", "type": "output",- "description": "Gate 2 output; NAND output Y = 2A·2B (IOL 8mA per operating conditions)"+ "description": "Gate 2 output; NAND output Y = 2A\u00b72B (IOL 8mA per operating conditions)" }, { "number": "7",@@ -110,37 +95,37 @@ "number": "8", "name": "3Y", "type": "output",- "description": "Gate 3 output; NAND output Y = 3A·3B (IOL 8mA per operating conditions)"+ "description": "Gate 3 output; NAND output Y = 3A\u00b73B (IOL 8mA per operating conditions)" }, { "number": "9", "name": "3B", "type": "input",- "description": "Gate 3 input B; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)"+ "description": "Gate 3 input B; TTL-compatible 2-input NAND input (VIH \u2265 2V, VIL \u2264 0.8V)" }, { "number": "10", "name": "3A", "type": "input",- "description": "Gate 3 input A; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)"+ "description": "Gate 3 input A; TTL-compatible 2-input NAND input (VIH \u2265 2V, VIL \u2264 0.8V)" }, { "number": "11", "name": "4Y", "type": "output",- "description": "Gate 4 output; NAND output Y = 4A·4B (IOL 8mA per operating conditions)"+ "description": "Gate 4 output; NAND output Y = 4A\u00b74B (IOL 8mA per operating conditions)" }, { "number": "12", "name": "4B", "type": "input",- "description": "Gate 4 input B; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)"+ "description": "Gate 4 input B; TTL-compatible 2-input NAND input (VIH \u2265 2V, VIL \u2264 0.8V)" }, { "number": "13", "name": "4A", "type": "input",- "description": "Gate 4 input A; TTL-compatible 2-input NAND input (VIH ≥ 2V, VIL ≤ 0.8V)"+ "description": "Gate 4 input A; TTL-compatible 2-input NAND input (VIH \u2265 2V, VIL \u2264 0.8V)" }, { "number": "14",@@ -183,10 +168,46 @@ "footprint": "viewers/footprint.html" } },- "visibility": "public",- "org": "adom",+ "metadata": {+ "specs": {+ "Manufacturer": "Texas Instruments",+ "Package": "SOP-14-208mil",+ "Category": "Logic",+ "Pins": "14"+ }+ },+ "variants": [],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74ls00nsr"+ ],+ "discovery_pitch": "SN74LS00NSR (Texas Instruments) component page: datasheet pinout, KiCad symbol, footprint and 3D.", "author": { "name": "Ray", "email": "[email protected]"- }+ },+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74ls00nsr.kicad_sym",+ "sn74ls00nsr.kicad_mod",+ "sn74ls00nsr.glb",+ "sn74ls00nsr.step",+ "sn74ls00nsr.lbr",+ "docs/hero.png",+ "docs/sn74ls00nsr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ] }
sn74ls00nsr-etched.glbadded⋯ 1 unchanged line ⋯
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