# SN74LS00N

**Texas Instruments** · Logic Gates · PDIP-14

SN74LS00N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A of the 2-input NAND gate; inputs are TTL compliant with VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 2 | 1B | input | Gate 1 input B of the 2-input NAND gate; inputs are TTL compliant with VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 3 | 1Y | output | Gate 1 NAND output, Y = A · B for positive logic. |
| 4 | 2A | input | Gate 2 input A of the 2-input NAND gate; inputs are TTL compliant with VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 5 | 2B | input | Gate 2 input B of the 2-input NAND gate; inputs are TTL compliant with VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 6 | 2Y | output | Gate 2 NAND output, Y = A · B for positive logic. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 3Y | output | Gate 3 NAND output, Y = A · B for positive logic. |
| 9 | 3B | input | Gate 3 input B of the 2-input NAND gate; inputs are TTL compliant with VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 10 | 3A | input | Gate 3 input A of the 2-input NAND gate; inputs are TTL compliant with VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 11 | 4Y | output | Gate 4 NAND output, Y = A · B for positive logic. |
| 12 | 4B | input | Gate 4 input B of the 2-input NAND gate; inputs are TTL compliant with VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 13 | 4A | input | Gate 4 input A of the 2-input NAND gate; inputs are TTL compliant with VIH of 2 V minimum and VIL of 0.8 V maximum. |
| 14 | VCC | power_in | Power supply; for SN74xx00 the recommended supply is 4.75 V to 5.25 V (5 V nominal). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level input voltage | VIH | 2 |  |  | V |  | 4 |
| Low-level input voltage | VIL |  |  | 0.8 | V | Row lists SNx400, SN7LS400, SNx4S00 (SN7LS400 printed; see review) | 4 |
| High-level output current | IOH |  |  | -0.4 | mA | SN5400, SN54LS00, SN74LS00 | 4 |
| Low-level output current | IOL |  |  | 8 | mA | Row printed as SN7LS400 (see review) | 4 |
| Operating free-air temperature | TA | 0 |  | 70 | °C | SN74xx00 | 5 |
| Supply voltage | VCC |  |  | 7 | V | Voltage values with respect to network ground terminal | 4 |
| Input voltage | VI |  |  | 7 | V | SNx4LS00 | 4 |
| Junction temperature | TJ |  |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Input clamp voltage | VIK |  |  | -1.5 | V | VCC = MIN and II = -18 mA | 6 |
| High-level output voltage | VOH | 2.5 | 3.4 |  | V | VCC = MIN, VIL = MAX, and IOH = -0.4 mA | 6 |
| Low-level output voltage | VOL |  | 0.25 | 0.4 | V | VCC = MIN and VIH = 2 V, IOL = 4 mA | 6 |
| Low-level output voltage | VOL |  | 0.35 | 0.5 | V | VCC = MIN and VIH = 2 V, IOL = 8 mA (SN74LS00) | 6 |
| Input current at maximum input voltage | II |  |  | 0.1 | mA | VCC = MAX and VI = 7 V | 6 |
| High-level input current | IIH |  |  | 20 | µA | VCC = MAX and VI = 2.7 V | 6 |
| Low-level input current | IIL |  |  | -0.4 | mA | VCC = MAX and VI = 0.4 V | 6 |
| Short-circuit output current | IOS |  | -20 | -100 | mA | VCC = MAX | 6 |
| Supply current, output high | ICCH |  | 0.8 | 1.6 | mA | VCC = MAX and VI = 0 V | 6 |
| Supply current, output low | ICCL |  | 2.4 | 4.4 | mA | VCC = MAX and VI = 4.5 V | 6 |
| Propagation delay time, low-to-high-level output | tPLH |  | 9 | 15 | ns | VCC = 5 V, TA = 25°C, RL = 2 kΩ, CL = 15 pF, A or B to Y | 7 |
| Propagation delay time, high-to-low-level output | tPHL |  | 10 | 15 | ns | VCC = 5 V, TA = 25°C, RL = 2 kΩ, CL = 15 pF, A or B to Y | 7 |
| Junction-to-ambient thermal resistance | RθJA |  | 54.8 |  | °C/W | N (PDIP) 14-pin package, JESD 51-7 | 6 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 42.1 |  | °C/W | N (PDIP) 14-pin package | 6 |
| Junction-to-board thermal resistance | RθJB |  | 34.8 |  | °C/W | N (PDIP) 14-pin package | 6 |

## CAD (KiCad official)

- Symbol: `SN74LS00N`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74ls00n-etched.step` / `sn74ls00n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ls00n.step` / `sn74ls00n.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74ls00) (40 pp, sha256 `ac4bbf6801413a20`, retrieved 2026-10-15, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74ls00n-datasheet.pdf)