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SN74HCT74N

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Texas Instruments Flip Flops, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74HCT74N

Texas Instruments · Flip Flops · PDIP-14

SN74HCT74N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLR input Active-low asynchronous clear for flip-flop 1; a low level resets the output regardless of other inputs.
2 1D input Data input of flip-flop 1, transferred to the output on the positive edge of CLK.
3 1CLK input Clock input of flip-flop 1, positive-edge triggered.
4 1PRE input Active-low asynchronous preset for flip-flop 1; a low level sets the output regardless of other inputs.
5 1Q output True output of flip-flop 1, driving up to ±4 mA at 5 V.
6 1Q̅ output Complementary output of flip-flop 1, driving up to ±4 mA at 5 V.
7 GND power_in Ground.
8 2Q̅ output Complementary output of flip-flop 2, driving up to ±4 mA at 5 V.
9 2Q output True output of flip-flop 2, driving up to ±4 mA at 5 V.
10 2PRE input Active-low asynchronous preset for flip-flop 2; a low level sets the output regardless of other inputs.
11 2CLK input Clock input of flip-flop 2, positive-edge triggered.
12 2D input Data input of flip-flop 2, transferred to the output on the positive edge of CLK.
13 2CLR input Active-low asynchronous clear for flip-flop 2; a low level resets the output regardless of other inputs.
14 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended, with a 0.1-µF bypass capacitor recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range (absolute maximum) VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Junction temperature TJ 150 °C 4
Storage temperature range Tstg -65 150 °C 4
Supply voltage VCC 4.5 5 5.5 V 4
High-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V 4
Low-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V 4
Input voltage VI 0 V 4
Output voltage VO 0 V 4
Input transition rise/fall time Δt/Δv 500 ns 4
Operating free-air temperature TA -40 85 °C 4
High-level output voltage VOH 4.4 V VI = VIH or VIL; IOH = −20 μA; VCC = 4.5 V 5
High-level output voltage VOH 3.84 V VI = VIH or VIL; IOH = −4 mA; VCC = 4.5 V 5
Low-level output voltage VOL 0.1 V VI = VIH or VIL; IOL = 20 μA; VCC = 4.5 V 5
Low-level output voltage VOL 0.33 V VI = VIH or VIL; IOL = 4 mA; VCC = 4.5 V 5
Input leakage current II -1000 1000 nA VI = VCC or 0; VCC = 5.5 V 5
Supply current ICC 40 μA VI = VCC or 0; IO = 0; VCC = 5.5 V 5
Additional supply current per input at TTL level ΔICC 2.9 mA One input at 0.5 V or 2.4 V; other inputs at 0 or VCC; VCC = 5.5 V 5
Input capacitance Ci 10 pF VCC = 4.5 V to 5.5 V 5
Clock frequency fclock 22 MHz VCC = 4.5 V 5
Clock frequency fclock 24 MHz VCC = 5.5 V 5
Pulse duration, PRE or CLR low tw 20 ns VCC = 4.5 V 5
Pulse duration, PRE or CLR low tw 18 ns VCC = 5.5 V 5
Pulse duration, CLK high or low tw 23 ns VCC = 4.5 V 5
Pulse duration, CLK high or low tw 21 ns VCC = 5.5 V 5
Setup time before CLK↑, data tsu 15 ns VCC = 4.5 V 5
Setup time before CLK↑, data tsu 14 ns VCC = 5.5 V 5
Setup time before CLK↑, PRE or CLR inactive tsu 0 ns VCC = 4.5 V 5
Hold time, data after CLK↑ th 0 ns VCC = 4.5 V 5
Maximum clock frequency (fmax) fmax 22 MHz CL = 50 pF; VCC = 4.5 V 6
Maximum clock frequency (fmax) fmax 24 MHz CL = 50 pF; VCC = 5.5 V 6
Propagation delay, PRE or CLR to Q or Q tpd 44 ns CL = 50 pF; VCC = 4.5 V 6
Propagation delay, PRE or CLR to Q or Q tpd 40 ns CL = 50 pF; VCC = 5.5 V 6
Propagation delay, CLK to Q or Q tpd 35 ns CL = 50 pF; VCC = 4.5 V 6
Propagation delay, CLK to Q or Q tpd 31 ns CL = 50 pF; VCC = 5.5 V 6
Output transition time, Q or Q tt 19 ns CL = 50 pF; VCC = 4.5 V 6
Output transition time, Q or Q tt 17 ns CL = 50 pF; VCC = 5.5 V 6
Junction-to-ambient thermal resistance (N, PDIP) RθJA 61.1 °C/W N (PDIP) 14-pin package 4
Junction-to-case (top) thermal resistance (N, PDIP) RθJC (top) 48.9 °C/W N (PDIP) 14-pin package 4
Junction-to-board thermal resistance (N, PDIP) RθJB 40.9 °C/W N (PDIP) 14-pin package 4

CAD (KiCad official)

  • Symbol: SN74HCT74N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74hct74n-etched.step / sn74hct74n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hct74n.step / sn74hct74n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 c2b53a743a33ebb8, retrieved 2026-10-16, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF