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SN74HCT595QPWRQ1
Public Made by Adomby adom
Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HCT595QPWRQ1
Texas Instruments · Shift Registers · TSSOP-16
SN74HCT595QPWRQ1 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | output | Parallel three-state output QB of the storage register; placed in high impedance when OE is high. |
| 2 | QC | output | Parallel three-state output QC of the storage register; placed in high impedance when OE is high. |
| 3 | QD | output | Parallel three-state output QD of the storage register; placed in high impedance when OE is high. |
| 4 | QE | output | Parallel three-state output QE of the storage register; placed in high impedance when OE is high. |
| 5 | QF | output | Parallel three-state output QF of the storage register; placed in high impedance when OE is high. |
| 6 | QG | output | Parallel three-state output QG of the storage register; placed in high impedance when OE is high. |
| 7 | QH | output | Parallel three-state output QH of the storage register; placed in high impedance when OE is high. |
| 8 | GND | power_in | Ground reference connection for the device. |
| 9 | QH' | output | Serial output of the shift register, used for cascading to the SER input of another device; not affected by the OE input. |
| 10 | SRCLR | input | Active-low direct clear of the shift register; a low level clears the shift register contents. |
| 11 | SRCLK | input | Shift register clock; data is shifted into the shift register on the rising edge. |
| 12 | RCLK | input | Storage register clock; data in the shift register is transferred to the storage/output register on the rising edge. |
| 13 | OE | input | Active-low output enable; when high, outputs QA through QH are disabled (high-impedance), and internal data and QH' are unaffected. |
| 14 | SER | input | Serial data input to the shift register. |
| 15 | QA | output | Parallel three-state output QA of the storage register; placed in high impedance when OE is high. |
| 16 | VCC | power_in | Positive supply voltage; recommended operating range is 4.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| High-level input voltage | VIH | 2 | V | VCC = 4.5V to 5.5V | 4 | ||
| Low-level input voltage | VIL | 0.8 | V | VCC = 4.5V to 5.5V | 4 | ||
| Input transition rise or fall rate | Δt/Δv | 500 | ns/V | VCC = 4.5V to 5.5V | 4 | ||
| Ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VCC + 0.5V | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC + 0.5V | 4 | |
| Continuous output current | IO | -35 | 35 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | ICC | -70 | 70 | mA | 4 | ||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| High-level output voltage | VOH | 4.4 | V | VI = VIH or VIL; IOH = -20uA; VCC = 4.5V; TA = 25°C | 5 | ||
| High-level output voltage | VOH | 3.98 | V | VI = VIH or VIL; IOH = -6mA; VCC = 4.5V; TA = 25°C | 5 | ||
| High-level output voltage | VOH | 3.84 | V | VI = VIH or VIL; IOH = -6mA; VCC = 4.5V; TA = -40°C to 125°C | 5 | ||
| Low-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; IOL = 20uA; VCC = 4.5V; TA = 25°C | 5 | ||
| Low-level output voltage | VOL | 0.26 | V | VI = VIH or VIL; IOL = 6mA; VCC = 4.5V; TA = 25°C | 5 | ||
| Low-level output voltage | VOL | 0.33 | V | VI = VIH or VIL; IOL = 6mA; VCC = 4.5V; TA = -40°C to 125°C | 5 | ||
| Input leakage current | II | -100 | 100 | nA | VI = VCC or 0; VCC = 5.5V; TA = 25°C | 5 | |
| Input leakage current | II | -1000 | 1000 | nA | VI = VCC or 0; VCC = 5.5V; TA = -40°C to 125°C | 5 | |
| Off-state (high-impedance) output current | IOZ | -0.5 | 0.5 | µA | VO = VCC or 0, QA-QH; VCC = 5.5V; TA = 25°C | 5 | |
| Off-state (high-impedance) output current | IOZ | -5 | 5 | µA | VO = VCC or 0, QA-QH; VCC = 5.5V; TA = -40°C to 125°C | 5 | |
| Supply current | ICC | 8 | µA | VI = VCC or 0, IO = 0; VCC = 5.5V; TA = 25°C | 5 | ||
| Supply current | ICC | 80 | µA | VI = VCC or 0, IO = 0; VCC = 5.5V; TA = -40°C to 125°C | 5 | ||
| Additional static supply current per input pin | ΔICC | 126.2 | µA | VI = VCC - 2.1V; VCC = 4.5V to 5.5V; TA = 25°C | 5 | ||
| Additional static supply current per input pin | ΔICC | 157.5 | µA | VI = VCC - 2.1V; VCC = 4.5V to 5.5V; TA = -40°C to 125°C | 5 | ||
| Additional static supply current per input pin | ΔICC | 2.4 | mA | VI = 0.5V or 2.4V; VCC = 5.5V; TA = 25°C | 5 | ||
| Additional static supply current per input pin | ΔICC | 2.9 | mA | VI = 0.5V or 2.4V; VCC = 5.5V; TA = -40°C to 125°C | 5 | ||
| Clock frequency | fclock | 25 | MHz | VCC = 4.5V; TA = -40°C to 125°C | 5 | ||
| Pulse duration, SRCLK or RCLK high or low | tw | 20 | ns | VCC = 4.5V; TA = -40°C to 125°C | 5 | ||
| Pulse duration, SRCLR low | tw | 20 | ns | VCC = 4.5V; TA = -40°C to 125°C | 5 | ||
| Setup time, SER before SRCLK rising | tsu | 25 | ns | VCC = 4.5V; TA = -40°C to 125°C | 6 | ||
| Setup time, SRCLK rising before RCLK rising | tsu | 20 | ns | VCC = 4.5V; TA = -40°C to 125°C | 6 | ||
| Setup time, SRCLR low before RCLK rising | tsu | 13 | ns | VCC = 4.5V; TA = -40°C to 125°C | 6 | ||
| Setup time, SRCLR high before SRCLK rising (inactive) | tsu | 12 | ns | VCC = 4.5V; TA = -40°C to 125°C | 6 | ||
| Hold time, SER after SRCLK rising | th | 0 | ns | VCC = 4.5V; TA = -40°C to 125°C | 6 | ||
| Propagation delay, SRCLK to QH' | tpd | 53 | ns | VCC = 4.5V; TA = -40°C to 125°C | 6 | ||
| Propagation delay, RCLK to QA-QH | tpd | 50 | ns | VCC = 4.5V; TA = -40°C to 125°C | 6 | ||
| Propagation delay, SRCLR to QH' | tPHL | 50 | ns | VCC = 4.5V; TA = -40°C to 125°C | 6 | ||
| Enable time, OE to QA-QH | ten | 44 | ns | VCC = 4.5V; TA = -40°C to 125°C | 6 | ||
| Disable time, OE to QA-QH | tdis | 38 | ns | VCC = 4.5V; TA = -40°C to 125°C | 6 | ||
| Transition time, any output | tt | 15 | ns | VCC = 4.5V; TA = -40°C to 125°C | 6 | ||
| Transition time, any output | tt | 17 | ns | VCC = 5.5V; TA = -40°C to 125°C | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 131.8 | °C/W | PW (TSSOP) 16-pin package | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 69.8 | °C/W | PW (TSSOP) 16-pin package | 4 | ||
| Junction-to-board thermal resistance | RθJB | 76.5 | °C/W | PW (TSSOP) 16-pin package | 4 |
CAD (KiCad official)
- Symbol:
SN74HCT595QPWRQ1 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74hct595qpwrq1-etched.step/sn74hct595qpwrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hct595qpwrq1.step/sn74hct595qpwrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
e48427033ac66b5b, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).