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SN74HCT573DWR

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Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74HCT573DWR

Texas Instruments · Latches · SOIC-20-300mil

SN74HCT573DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output-enable input; high places the eight Q outputs in the high-impedance state, low enables them, and it does not affect the latches' internal operation.
2 1D input Data input for latch 1, transparent to 1Q while LE is high and latched when LE is low.
3 2D input Data input for latch 2, transparent to 2Q while LE is high and latched when LE is low.
4 3D input Data input for latch 3, transparent to 3Q while LE is high and latched when LE is low.
5 4D input Data input for latch 4, transparent to 4Q while LE is high and latched when LE is low.
6 5D input Data input for latch 5, transparent to 5Q while LE is high and latched when LE is low.
7 6D input Data input for latch 6, transparent to 6Q while LE is high and latched when LE is low.
8 7D input Data input for latch 7, transparent to 7Q while LE is high and latched when LE is low.
9 8D input Data input for latch 8, transparent to 8Q while LE is high and latched when LE is low.
10 GND power_in Ground reference for the device; continuous current through VCC or GND is limited to ±70 mA.
11 LE input Latch-enable input; outputs follow the D inputs while high and retain the data set up at D when low.
12 8Q tri_state 3-state output of latch 8 with ±6 mA drive at 5 V, high-impedance when OE is high.
13 7Q tri_state 3-state output of latch 7 with ±6 mA drive at 5 V, high-impedance when OE is high.
14 6Q tri_state 3-state output of latch 6 with ±6 mA drive at 5 V, high-impedance when OE is high.
15 5Q tri_state 3-state output of latch 5 with ±6 mA drive at 5 V, high-impedance when OE is high.
16 4Q tri_state 3-state output of latch 4 with ±6 mA drive at 5 V, high-impedance when OE is high.
17 3Q tri_state 3-state output of latch 3 with ±6 mA drive at 5 V, high-impedance when OE is high.
18 2Q tri_state 3-state output of latch 2 with ±6 mA drive at 5 V, high-impedance when OE is high.
19 1Q tri_state 3-state output of latch 1 with ±6 mA drive at 5 V, high-impedance when OE is high.
20 VCC power_in Supply voltage pin, recommended 4.5 V to 5.5 V (absolute maximum 7 V), with a 0.1-µF bypass capacitor recommended close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74HCT573DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74hct573dwr-etched.step / sn74hct573dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hct573dwr.step / sn74hct573dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 989f5f298ade3a5b, retrieved 2026-10-06, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF