component
SN74HCT541N
Public Made by Adomby adom
TI(德州仪器) Buffers, Drivers, Receivers, Transceivers, DIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SN74HCT541N
TI(德州仪器) · Buffers, Drivers, Receivers, Transceivers · DIP-20
SN74HCT541N from TI(德州仪器), in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Output enable 1; when OE1 or OE2 is high, all eight outputs are forced to the high-impedance state, so outputs are active only when both enables are low. |
| 2 | A1 | input | Data input for buffer channel 1, passed non-inverted to Y1 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 3 | A2 | input | Data input for buffer channel 2, passed non-inverted to Y2 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 4 | A3 | input | Data input for buffer channel 3, passed non-inverted to Y3 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 5 | A4 | input | Data input for buffer channel 4, passed non-inverted to Y4 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 6 | A5 | input | Data input for buffer channel 5, passed non-inverted to Y5 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 7 | A6 | input | Data input for buffer channel 6, passed non-inverted to Y6 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 8 | A7 | input | Data input for buffer channel 7, passed non-inverted to Y7 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 9 | A8 | input | Data input for buffer channel 8, passed non-inverted to Y8 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | Y8 | tri_state | Three-state buffered output of channel 8 that follows A8 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 12 | Y7 | tri_state | Three-state buffered output of channel 7 that follows A7 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 13 | Y6 | tri_state | Three-state buffered output of channel 6 that follows A6 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 14 | Y5 | tri_state | Three-state buffered output of channel 5 that follows A5 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 15 | Y4 | tri_state | Three-state buffered output of channel 4 that follows A4 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 16 | Y3 | tri_state | Three-state buffered output of channel 3 that follows A3 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 17 | Y2 | tri_state | Three-state buffered output of channel 2 that follows A2 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 18 | Y1 | tri_state | Three-state buffered output of channel 1 that follows A1 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 19 | OE2 | input | Output enable 2; when OE2 or OE1 is high, all eight outputs are forced to the high-impedance state, so outputs are active only when both enables are low. |
| 20 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V recommended (5 V nominal), with a 0.1-µF bypass capacitor placed as close to the pin as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TI(德州仪器) |
| Package | DIP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VCC | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC | 4 | |
| Continuous output current | IO | -35 | 35 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -70 | 70 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature range | Tstg | -65 | 150 | °C | 4 | ||
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| High-level input voltage | VIH | 2 | V | VCC = 4.5 V to 5.5 V | 4 | ||
| Low-level input voltage | VIL | 0.8 | V | VCC = 4.5 V to 5.5 V | 4 | ||
| Input voltage | VI | 0 | V | 4 | |||
| Output voltage | VO | 0 | V | 4 | |||
| Input transition rise and fall time | ∆t/∆v | 500 | ns | 4 | |||
| Operating free-air temperature | TA | -40 | 85 | °C | 4 | ||
| High-level output voltage | VOH | 4.4 | 4.499 | V | VI = VIH or VIL; IOH = −20 µA; VCC = 4.5 V | 5 | |
| High-level output voltage | VOH | 3.84 | 4.3 | V | VI = VIH or VIL; IOH = −6 mA; VCC = 4.5 V | 5 | |
| Low-level output voltage | VOL | 0.001 | 0.1 | V | VI = VIH or VIL; IOL = 20 µA; VCC = 4.5 V | 5 | |
| Low-level output voltage | VOL | 0.17 | 0.33 | V | VI = VIH or VIL; IOL = 6 mA; VCC = 4.5 V | 5 | |
| Input leakage current | II | -1000 | 0.1 | 1000 | nA | VI = VCC or 0; VCC = 5.5 V | 5 |
| Off-state (high-impedance) output current | IOZ | -5 | 0.01 | 5 | µA | VO = VCC or 0; VI = VIH or VIL; VCC = 5.5 V | 5 |
| Supply current | ICC | 8 | 80 | µA | VI = VCC or 0; IO = 0; VCC = 5.5 V | 5 | |
| Supply current increase per TTL-level input | ∆ICC | 1.4 | 2.9 | mA | One input at 0.5 V or 2.4 V, other inputs at 0 or VCC; VCC = 5.5 V | 5 | |
| Input capacitance | Ci | 3 | 10 | pF | VCC = 4.5 V to 5.5 V | 5 | |
| Propagation delay A to Y | tpd | 13 | 29 | ns | CL = 50 pF; VCC = 4.5 V; A to Y | 5 | |
| Propagation delay A to Y | tpd | 12 | 26 | ns | CL = 50 pF; VCC = 5.5 V; A to Y | 5 | |
| Enable time OE to Y | ten | 21 | 38 | ns | CL = 50 pF; VCC = 4.5 V; OE to Y | 5 | |
| Enable time OE to Y | ten | 19 | 34 | ns | CL = 50 pF; VCC = 5.5 V; OE to Y | 5 | |
| Disable time OE to Y | tdis | 19 | 38 | ns | CL = 50 pF; VCC = 4.5 V; OE to Y | 5 | |
| Disable time OE to Y | tdis | 18 | 34 | ns | CL = 50 pF; VCC = 5.5 V; OE to Y | 5 | |
| Output transition time Y | tt | 8 | 15 | ns | CL = 50 pF; VCC = 4.5 V; Y | 5 | |
| Output transition time Y | tt | 7 | 14 | ns | CL = 50 pF; VCC = 5.5 V; Y | 5 | |
| Propagation delay A to Y | tpd | 20 | 42 | ns | CL = 150 pF; VCC = 4.5 V; A to Y | 5 | |
| Propagation delay A to Y | tpd | 19 | 38 | ns | CL = 150 pF; VCC = 5.5 V; A to Y | 5 | |
| Enable time OE to Y | ten | 26 | 50 | ns | CL = 150 pF; VCC = 4.5 V; OE to Y | 5 | |
| Enable time OE to Y | ten | 25 | 45 | ns | CL = 150 pF; VCC = 5.5 V; OE to Y | 5 | |
| Output transition time Y | tt | 17 | 53 | ns | CL = 150 pF; VCC = 4.5 V; Y | 5 | |
| Output transition time Y | tt | 14 | 48 | ns | CL = 150 pF; VCC = 5.5 V; Y | 5 | |
| Junction-to-ambient thermal resistance | RθJA | 84.6 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 72.5 | °C/W | 4 | |||
| Junction-to-board thermal resistance | RθJB | 65.3 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
SN74HCT541N - Footprint:
Package_DIP:DIP-20_W7.62mm - 3D model: DIP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74hct541n-etched.step/sn74hct541n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hct541n.step/sn74hct541n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TI(德州仪器) datasheet (30 pp, sha256
429686d50f7863c5, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HCT541N
**TI(德州仪器)** · Buffers, Drivers, Receivers, Transceivers · DIP-20
SN74HCT541N from TI(德州仪器), in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Output enable 1; when OE1 or OE2 is high, all eight outputs are forced to the high-impedance state, so outputs are active only when both enables are low. |
| 2 | A1 | input | Data input for buffer channel 1, passed non-inverted to Y1 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 3 | A2 | input | Data input for buffer channel 2, passed non-inverted to Y2 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 4 | A3 | input | Data input for buffer channel 3, passed non-inverted to Y3 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 5 | A4 | input | Data input for buffer channel 4, passed non-inverted to Y4 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 6 | A5 | input | Data input for buffer channel 5, passed non-inverted to Y5 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 7 | A6 | input | Data input for buffer channel 6, passed non-inverted to Y6 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 8 | A7 | input | Data input for buffer channel 7, passed non-inverted to Y7 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 9 | A8 | input | Data input for buffer channel 8, passed non-inverted to Y8 when the outputs are enabled; inputs must stay between 0 V and VCC and unused inputs must be tied to VCC or GND. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | Y8 | tri_state | Three-state buffered output of channel 8 that follows A8 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 12 | Y7 | tri_state | Three-state buffered output of channel 7 that follows A7 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 13 | Y6 | tri_state | Three-state buffered output of channel 6 that follows A6 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 14 | Y5 | tri_state | Three-state buffered output of channel 5 that follows A5 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 15 | Y4 | tri_state | Three-state buffered output of channel 4 that follows A4 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 16 | Y3 | tri_state | Three-state buffered output of channel 3 that follows A3 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 17 | Y2 | tri_state | Three-state buffered output of channel 2 that follows A2 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 18 | Y1 | tri_state | Three-state buffered output of channel 1 that follows A1 and can drive up to 15 LSTTL loads (±6 mA at 5 V); it is high impedance when OE1 or OE2 is high. |
| 19 | OE2 | input | Output enable 2; when OE2 or OE1 is high, all eight outputs are forced to the high-impedance state, so outputs are active only when both enables are low. |
| 20 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V recommended (5 V nominal), with a 0.1-µF bypass capacitor placed as close to the pin as possible. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TI(德州仪器) |
| Package | DIP-20 |
| Category | Logic |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | | 7 | V | | 4 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < 0 or VI > VCC | 4 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < 0 or VO > VCC | 4 |
| Continuous output current | IO | -35 | | 35 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND | | -70 | | 70 | mA | | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Storage temperature range | Tstg | -65 | | 150 | °C | | 4 |
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | | 4 |
| High-level input voltage | VIH | 2 | | | V | VCC = 4.5 V to 5.5 V | 4 |
| Low-level input voltage | VIL | | | 0.8 | V | VCC = 4.5 V to 5.5 V | 4 |
| Input voltage | VI | 0 | | | V | | 4 |
| Output voltage | VO | 0 | | | V | | 4 |
| Input transition rise and fall time | ∆t/∆v | | | 500 | ns | | 4 |
| Operating free-air temperature | TA | -40 | | 85 | °C | | 4 |
| High-level output voltage | VOH | 4.4 | 4.499 | | V | VI = VIH or VIL; IOH = −20 µA; VCC = 4.5 V | 5 |
| High-level output voltage | VOH | 3.84 | 4.3 | | V | VI = VIH or VIL; IOH = −6 mA; VCC = 4.5 V | 5 |
| Low-level output voltage | VOL | | 0.001 | 0.1 | V | VI = VIH or VIL; IOL = 20 µA; VCC = 4.5 V | 5 |
| Low-level output voltage | VOL | | 0.17 | 0.33 | V | VI = VIH or VIL; IOL = 6 mA; VCC = 4.5 V | 5 |
| Input leakage current | II | -1000 | 0.1 | 1000 | nA | VI = VCC or 0; VCC = 5.5 V | 5 |
| Off-state (high-impedance) output current | IOZ | -5 | 0.01 | 5 | µA | VO = VCC or 0; VI = VIH or VIL; VCC = 5.5 V | 5 |
| Supply current | ICC | | 8 | 80 | µA | VI = VCC or 0; IO = 0; VCC = 5.5 V | 5 |
| Supply current increase per TTL-level input | ∆ICC | | 1.4 | 2.9 | mA | One input at 0.5 V or 2.4 V, other inputs at 0 or VCC; VCC = 5.5 V | 5 |
| Input capacitance | Ci | | 3 | 10 | pF | VCC = 4.5 V to 5.5 V | 5 |
| Propagation delay A to Y | tpd | | 13 | 29 | ns | CL = 50 pF; VCC = 4.5 V; A to Y | 5 |
| Propagation delay A to Y | tpd | | 12 | 26 | ns | CL = 50 pF; VCC = 5.5 V; A to Y | 5 |
| Enable time OE to Y | ten | | 21 | 38 | ns | CL = 50 pF; VCC = 4.5 V; OE to Y | 5 |
| Enable time OE to Y | ten | | 19 | 34 | ns | CL = 50 pF; VCC = 5.5 V; OE to Y | 5 |
| Disable time OE to Y | tdis | | 19 | 38 | ns | CL = 50 pF; VCC = 4.5 V; OE to Y | 5 |
| Disable time OE to Y | tdis | | 18 | 34 | ns | CL = 50 pF; VCC = 5.5 V; OE to Y | 5 |
| Output transition time Y | tt | | 8 | 15 | ns | CL = 50 pF; VCC = 4.5 V; Y | 5 |
| Output transition time Y | tt | | 7 | 14 | ns | CL = 50 pF; VCC = 5.5 V; Y | 5 |
| Propagation delay A to Y | tpd | | 20 | 42 | ns | CL = 150 pF; VCC = 4.5 V; A to Y | 5 |
| Propagation delay A to Y | tpd | | 19 | 38 | ns | CL = 150 pF; VCC = 5.5 V; A to Y | 5 |
| Enable time OE to Y | ten | | 26 | 50 | ns | CL = 150 pF; VCC = 4.5 V; OE to Y | 5 |
| Enable time OE to Y | ten | | 25 | 45 | ns | CL = 150 pF; VCC = 5.5 V; OE to Y | 5 |
| Output transition time Y | tt | | 17 | 53 | ns | CL = 150 pF; VCC = 4.5 V; Y | 5 |
| Output transition time Y | tt | | 14 | 48 | ns | CL = 150 pF; VCC = 5.5 V; Y | 5 |
| Junction-to-ambient thermal resistance | RθJA | | 84.6 | | °C/W | | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 72.5 | | °C/W | | 4 |
| Junction-to-board thermal resistance | RθJB | | 65.3 | | °C/W | | 4 |
## CAD (KiCad official)
- Symbol: `SN74HCT541N`
- Footprint: `Package_DIP:DIP-20_W7.62mm`
- 3D model: DIP-20 (KiCad packages3D, STEP)
- 3D model files: `sn74hct541n-etched.step` / `sn74hct541n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hct541n.step` / `sn74hct541n.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TI(德州仪器) datasheet](https://www.ti.com/cn/lit/gpn/sn74hct541) (30 pp, sha256 `429686d50f7863c5`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hct541n-datasheet.pdf)