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SN74HCT540N

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Texas Instruments Buffers / Drivers, PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74HCT540N

Texas Instruments · Buffers / Drivers · PDIP-20

SN74HCT540N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Output-enable 1 input; if either OE1 or OE2 is high, all eight outputs are in the high-impedance state.
2 A1 input Data input A1, TTL-voltage compatible, inverted at output Y1.
3 A2 input Data input A2, TTL-voltage compatible, inverted at output Y2.
4 A3 input Data input A3, TTL-voltage compatible, inverted at output Y3.
5 A4 input Data input A4, TTL-voltage compatible, inverted at output Y4.
6 A5 input Data input A5, TTL-voltage compatible, inverted at output Y5.
7 A6 input Data input A6, TTL-voltage compatible, inverted at output Y6.
8 A7 input Data input A7, TTL-voltage compatible, inverted at output Y7.
9 A8 input Data input A8, TTL-voltage compatible, inverted at output Y8.
10 GND power_in Ground pin.
11 Y8 tri_state 3-state inverting output for A8, with ±6 mA drive at 5 V.
12 Y7 tri_state 3-state inverting output for A7, with ±6 mA drive at 5 V.
13 Y6 tri_state 3-state inverting output for A6, with ±6 mA drive at 5 V.
14 Y5 tri_state 3-state inverting output for A5, with ±6 mA drive at 5 V.
15 Y4 tri_state 3-state inverting output for A4, with ±6 mA drive at 5 V.
16 Y3 tri_state 3-state inverting output for A3, with ±6 mA drive at 5 V.
17 Y2 tri_state 3-state inverting output for A2, with ±6 mA drive at 5 V.
18 Y1 tri_state 3-state inverting output for A1, with ±6 mA drive at 5 V.
19 OE2 input Output-enable 2 input; if either OE1 or OE2 is high, all eight outputs are in the high-impedance state.
20 VCC power_in Supply voltage, 4.5 V to 5.5 V operating range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level output voltage VOH 4.4 4.499 V VI=VIH or VIL, IOH=-20 µA, VCC=4.5 V 3
High-level output voltage VOH 3.84 4.3 V VI=VIH or VIL, IOH=-6 mA, VCC=4.5 V 3
Low-level output voltage VOL 0.001 0.1 V VI=VIH or VIL, IOL=20 µA, VCC=4.5 V 3
Low-level output voltage VOL 0.17 0.33 V VI=VIH or VIL, IOL=6 mA, VCC=4.5 V 3
Input current II -1000 1000 nA VI=VCC or 0, VCC=5.5 V 3
Off-state output current IOZ -5 5 µA VO=VCC or 0, VI=VIH or VIL, VCC=5.5 V 3
Supply current ICC 8 80 µA VI=VCC or 0, IO=0, VCC=5.5 V 3
Additional supply current per input ΔICC 1.4 2.9 mA One input at 0.5 V or 2.4 V, other inputs at 0 or VCC, VCC=5.5 V 3
Input capacitance Ci 3 10 pF VCC=4.5 V to 5.5 V 3
Propagation delay A to Y tpd 13 25 ns VCC=4.5 V, CL=50 pF 3
Propagation delay A to Y tpd 12 23 ns VCC=5.5 V, CL=50 pF 3
Enable time OE to Y ten 20 38 ns VCC=4.5 V, CL=50 pF 3
Enable time OE to Y ten 18 34 ns VCC=5.5 V, CL=50 pF 3
Disable time OE to Y tdis 19 38 ns VCC=4.5 V, CL=50 pF 3
Disable time OE to Y tdis 18 34 ns VCC=5.5 V, CL=50 pF 3
Output transition time tt 8 15 ns VCC=4.5 V, CL=50 pF 3
Output transition time tt 7 14 ns VCC=5.5 V, CL=50 pF 3
Propagation delay A to Y tpd 20 38 ns VCC=4.5 V, CL=150 pF 3
Propagation delay A to Y tpd 19 34 ns VCC=5.5 V, CL=150 pF 3
Enable time OE to Y ten 26 50 ns VCC=4.5 V, CL=150 pF 3
Enable time OE to Y ten 25 45 ns VCC=5.5 V, CL=150 pF 3
Output transition time tt 17 53 ns VCC=4.5 V, CL=150 pF 3
Output transition time tt 14 48 ns VCC=5.5 V, CL=150 pF 3
Power dissipation capacitance per buffer/driver Cpd 35 pF No load, TA=25°C 3
Supply voltage VCC 4.5 5 5.5 V 2
High-level input voltage VIH 2 V VCC=4.5 V to 5.5 V 2
Low-level input voltage VIL 0.8 V VCC=4.5 V to 5.5 V 2
Input voltage VI 0 5.5 V 0 to VCC 2
Output voltage VO 0 5.5 V 0 to VCC 2
Input transition (rise and fall) time tt 500 ns 2
Operating free-air temperature TA -40 85 °C 2
Supply voltage range VCC -0.5 7 V 2
Input clamp current IIK -20 20 mA VI<0 or VI>VCC 2
Output clamp current IOK -20 20 mA VO<0 or VO>VCC 2
Continuous output current IO -35 35 mA VO=0 to VCC 2
Continuous current through VCC or GND ICC -70 70 mA 2
Storage temperature range Tstg -65 150 °C 2
Package thermal impedance, N package θJA 69 °C/W N package, JESD 51-7 2

CAD (KiCad official)

  • Symbol: SN74HCT540N
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: PDIP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74hct540n-etched.step / sn74hct540n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hct540n.step / sn74hct540n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 4127bdaaad1a8ace, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF