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SN74HCT374N

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Texas Instruments Flip Flops, DIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74HCT374N

Texas Instruments · Flip Flops · DIP-20

SN74HCT374N from Texas Instruments, in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output enable that places the eight outputs in normal logic state or high-impedance state without affecting flip-flop internal operation.
2 1Q tri_state 3-state output of flip-flop 1, set to the level at 1D on the rising CLK edge.
3 1D input Data input for flip-flop 1, captured on the positive transition of CLK.
4 2D input Data input for flip-flop 2, captured on the positive transition of CLK.
5 2Q tri_state 3-state output of flip-flop 2, set to the level at 2D on the rising CLK edge.
6 3Q tri_state 3-state output of flip-flop 3, set to the level at 3D on the rising CLK edge.
7 3D input Data input for flip-flop 3, captured on the positive transition of CLK.
8 4D input Data input for flip-flop 4, captured on the positive transition of CLK.
9 4Q tri_state 3-state output of flip-flop 4, set to the level at 4D on the rising CLK edge.
10 GND power_in Ground pin.
11 CLK input Clock input; Q outputs take the D input levels on the positive transition.
12 5Q tri_state 3-state output of flip-flop 5, set to the level at 5D on the rising CLK edge.
13 5D input Data input for flip-flop 5, captured on the positive transition of CLK.
14 6D input Data input for flip-flop 6, captured on the positive transition of CLK.
15 6Q tri_state 3-state output of flip-flop 6, set to the level at 6D on the rising CLK edge.
16 7Q tri_state 3-state output of flip-flop 7, set to the level at 7D on the rising CLK edge.
17 7D input Data input for flip-flop 7, captured on the positive transition of CLK.
18 8D input Data input for flip-flop 8, captured on the positive transition of CLK.
19 8Q tri_state 3-state output of flip-flop 8, set to the level at 8D on the rising CLK edge.
20 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended (absolute maximum 7 V), with a 0.1-uF bypass capacitor recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74HCT374N
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: DIP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74hct374n-etched.step / sn74hct374n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hct374n.step / sn74hct374n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 d6967f49e2d44280, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF