# SN74HCT32N

**Texas Instruments** · Logic Gates · PDIP-14

SN74HCT32N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input A of gate 1 (Y = A + B); unused inputs must be held at VCC or GND, not left floating. |
| 2 | 1B | input | Input B of gate 1 (Y = A + B); unused inputs must be held at VCC or GND, not left floating. |
| 3 | 1Y | output | Output of gate 1; continuous output current is limited to ±25 mA (Absolute Maximum Ratings). |
| 4 | 2A | input | Input A of gate 2 (Y = A + B); unused inputs must be held at VCC or GND, not left floating. |
| 5 | 2B | input | Input B of gate 2 (Y = A + B); unused inputs must be held at VCC or GND, not left floating. |
| 6 | 2Y | output | Output of gate 2; continuous output current is limited to ±25 mA (Absolute Maximum Ratings). |
| 7 | GND | power_in | Ground reference; continuous current through VCC or GND is limited to ±50 mA. |
| 8 | 3Y | output | Output of gate 3; continuous output current is limited to ±25 mA (Absolute Maximum Ratings). |
| 9 | 3A | input | Input A of gate 3 (Y = A + B); unused inputs must be held at VCC or GND, not left floating. |
| 10 | 3B | input | Input B of gate 3 (Y = A + B); unused inputs must be held at VCC or GND, not left floating. |
| 11 | 4Y | output | Output of gate 4; continuous output current is limited to ±25 mA (Absolute Maximum Ratings). |
| 12 | 4A | input | Input A of gate 4 (Y = A + B); unused inputs must be held at VCC or GND, not left floating. |
| 13 | 4B | input | Input B of gate 4 (Y = A + B); unused inputs must be held at VCC or GND, not left floating. |
| 14 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V recommended; a 0.1-µF bypass capacitor is recommended close to this pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Absolute maximum supply voltage VCC | VCC | -0.5 |  | 7 | V |  | 4 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < 0 or VI > VCC | 4 |
| Output clamp current | IOK | -20 |  | 20 | mA | VO < 0 or VO > VCC | 4 |
| Continuous output current | IO | -25 |  | 25 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND |  | -50 |  | 50 | mA |  | 4 |
| Junction temperature | TJ |  |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V |  | 4 |
| High-level input voltage | VIH | 2 |  |  | V | VCC = 4.5 V to 5.5 V | 4 |
| Low-level input voltage | VIL |  |  | 0.8 | V | VCC = 4.5 V to 5.5 V | 4 |
| Input voltage | VI | 0 |  |  | V |  | 4 |
| Output voltage | VO | 0 |  |  | V |  | 4 |
| Input transition rise/fall time | tt |  |  | 500 | ns |  | 4 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 4 |
| Junction-to-ambient thermal resistance (N PDIP) | RθJA |  | 67 |  | °C/W |  | 4 |
| Junction-to-case (top) thermal resistance (N PDIP) | RθJC (top) |  | 55 |  | °C/W |  | 4 |
| Junction-to-board thermal resistance (N PDIP) | RθJB |  | 46.7 |  | °C/W |  | 4 |
| High-level output voltage | VOH | 4.4 | 4.499 |  | V | IOH = -20 μA, VCC = 4.5 V | 5 |
| High-level output voltage | VOH | 3.84 | 4.3 |  | V | IOH = -4 mA, VCC = 4.5 V | 5 |
| Low-level output voltage | VOL |  | 0.001 | 0.1 | V | IOL = 20 μA, VCC = 4.5 V | 5 |
| Low-level output voltage | VOL |  | 0.17 | 0.33 | V | IOL = 4 mA, VCC = 4.5 V | 5 |
| Input hold current | II | -1000 |  | 1000 | nA | VI = VCC or 0, VCC = 5.5 V | 5 |
| Supply current | ICC |  | 2 | 20 | μA | VI = VCC or 0, IO = 0, VCC = 5.5 V | 5 |
| Supply-current change | ΔICC |  | 1.4 | 2.9 | mA | One input at 0.5 V or 2.4 V, other inputs at 0 or VCC, VCC = 5.5 V | 5 |
| Input capacitance | Ci |  | 3 | 10 | pF | VCC = 4.5 V to 5.5 V | 5 |
| Propagation delay A or B to Y | tpd |  | 15 | 30 | ns | CL = 50 pF, VCC = 4.5 V | 5 |
| Propagation delay A or B to Y | tpd |  | 13 | 27 | ns | CL = 50 pF, VCC = 5.5 V | 5 |
| Transition time Y | tt |  | 9 | 19 | ns | CL = 50 pF, VCC = 4.5 V | 5 |
| Transition time Y | tt |  | 8 | 17 | ns | CL = 50 pF, VCC = 5.5 V | 5 |

## CAD (KiCad official)

- Symbol: `SN74HCT32N`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74hct32n-etched.step` / `sn74hct32n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hct32n.step` / `sn74hct32n.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hct32) (26 pp, sha256 `420bfc6c0e42206a`, retrieved 2026-10-15, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74hct32n-datasheet.pdf)