SN74HCT273DWR

{
  "slug": "sn74hct273dwr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Flip Flops, SOIC-20-300mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "sn74hct273dwr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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  "files": [
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    "README.md",
    "sn74hct273dwr.kicad_sym",
    "sn74hct273dwr.kicad_mod",
    "sn74hct273dwr.glb",
    "sn74hct273dwr.step",
    "sn74hct273dwr.lbr",
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    "docs/sn74hct273dwr-datasheet.pdf",
    "viewers/symbol.html",
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  "component": {
    "mpn": "SN74HCT273DWR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-20-300mil",
    "pin_count": 20,
    "category": "Logic",
    "subcategory": "Flip Flops",
    "datasheet": "https://www.ti.com/cn/lit/gpn/sn74hct273",
    "parts": {
      "symbol": "sn74hct273dwr.kicad_sym",
      "footprint": "sn74hct273dwr.kicad_mod",
      "model_3d": "sn74hct273dwr-etched.glb",
      "model_3d_plain": "sn74hct273dwr.glb",
      "model_3d_step": "sn74hct273dwr-etched.step",
      "model_3d_step_plain": "sn74hct273dwr.step",
      "lbr": "sn74hct273dwr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2652822"
    },
    "pins": [
      {
        "number": "1",
        "name": "CLR",
        "type": "input",
        "description": "Asynchronous clear input, active low; clears all flip-flop outputs to logic low."
      },
      {
        "number": "2",
        "name": "1Q",
        "type": "output",
        "description": "Channel 1 Q output; provides the latched logic state from the D flip-flop."
      },
      {
        "number": "3",
        "name": "1D",
        "type": "input",
        "description": "Channel 1 D input; data sampled at rising edge of CLK when CLR is high."
      },
      {
        "number": "4",
        "name": "2D",
        "type": "input",
        "description": "Channel 2 D input; data sampled at rising edge of CLK when CLR is high."
      },
      {
        "number": "5",
        "name": "2Q",
        "type": "output",
        "description": "Channel 2 Q output; provides the latched logic state from the D flip-flop."
      },
      {
        "number": "6",
        "name": "3Q",
        "type": "output",
        "description": "Channel 3 Q output; provides the latched logic state from the D flip-flop."
      },
      {
        "number": "7",
        "name": "3D",
        "type": "input",
        "description": "Channel 3 D input; data sampled at rising edge of CLK when CLR is high."
      },
      {
        "number": "8",
        "name": "4D",
        "type": "input",
        "description": "Channel 4 D input; data sampled at rising edge of CLK when CLR is high."
      },
      {
        "number": "9",
        "name": "4Q",
        "type": "output",
        "description": "Channel 4 Q output; provides the latched logic state from the D flip-flop."
      },
      {
        "number": "10",
        "name": "GND",
        "type": "power_in",
        "description": "Ground; device power supply return path."
      },
      {
        "number": "11",
        "name": "CLK",
        "type": "input",
        "description": "Clock input for all channels, rising edge triggered; samples all D inputs when CLR is high."
      },
      {
        "number": "12",
        "name": "5Q",
        "type": "output",
        "description": "Channel 5 Q output; provides the latched logic state from the D flip-flop."
      },
      {
        "number": "13",
        "name": "5D",
        "type": "input",
        "description": "Channel 5 D input; data sampled at rising edge of CLK when CLR is high."
      },
      {
        "number": "14",
        "name": "6D",
        "type": "input",
        "description": "Channel 6 D input; data sampled at rising edge of CLK when CLR is high."
      },
      {
        "number": "15",
        "name": "6Q",
        "type": "output",
        "description": "Channel 6 Q output; provides the latched logic state from the D flip-flop."
      },
      {
        "number": "16",
        "name": "7Q",
        "type": "output",
        "description": "Channel 7 Q output; provides the latched logic state from the D flip-flop."
      },
      {
        "number": "17",
        "name": "7D",
        "type": "input",
        "description": "Channel 7 D input; data sampled at rising edge of CLK when CLR is high."
      },
      {
        "number": "18",
        "name": "8D",
        "type": "input",
        "description": "Channel 8 D input; data sampled at rising edge of CLK when CLR is high."
      },
      {
        "number": "19",
        "name": "8Q",
        "type": "output",
        "description": "Channel 8 Q output; provides the latched logic state from the D flip-flop."
      },
      {
        "number": "20",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive power supply; operating range 4.5V to 5.5V per recommended operating conditions."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.2",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.2",
        "primary_model": "claude-haiku-4-5-20251001",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [],
        "pages_sent": 28,
        "cost_usd": 0.212,
        "at": "2026-09-23T17:52:39"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/sn74hct273",
        "pages": 28,
        "sha256": "be4aa8926dc70c63",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 20,
        "described": 20,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
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}