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SN74HCT273DWR
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74HCT273DWR
Texas Instruments · Flip Flops · SOIC-20-300mil
SN74HCT273DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Asynchronous clear input, active low; clears all flip-flop outputs to logic low. |
| 2 | 1Q | output | Channel 1 Q output; provides the latched logic state from the D flip-flop. |
| 3 | 1D | input | Channel 1 D input; data sampled at rising edge of CLK when CLR is high. |
| 4 | 2D | input | Channel 2 D input; data sampled at rising edge of CLK when CLR is high. |
| 5 | 2Q | output | Channel 2 Q output; provides the latched logic state from the D flip-flop. |
| 6 | 3Q | output | Channel 3 Q output; provides the latched logic state from the D flip-flop. |
| 7 | 3D | input | Channel 3 D input; data sampled at rising edge of CLK when CLR is high. |
| 8 | 4D | input | Channel 4 D input; data sampled at rising edge of CLK when CLR is high. |
| 9 | 4Q | output | Channel 4 Q output; provides the latched logic state from the D flip-flop. |
| 10 | GND | power_in | Ground; device power supply return path. |
| 11 | CLK | input | Clock input for all channels, rising edge triggered; samples all D inputs when CLR is high. |
| 12 | 5Q | output | Channel 5 Q output; provides the latched logic state from the D flip-flop. |
| 13 | 5D | input | Channel 5 D input; data sampled at rising edge of CLK when CLR is high. |
| 14 | 6D | input | Channel 6 D input; data sampled at rising edge of CLK when CLR is high. |
| 15 | 6Q | output | Channel 6 Q output; provides the latched logic state from the D flip-flop. |
| 16 | 7Q | output | Channel 7 Q output; provides the latched logic state from the D flip-flop. |
| 17 | 7D | input | Channel 7 D input; data sampled at rising edge of CLK when CLR is high. |
| 18 | 8D | input | Channel 8 D input; data sampled at rising edge of CLK when CLR is high. |
| 19 | 8Q | output | Channel 8 Q output; provides the latched logic state from the D flip-flop. |
| 20 | VCC | power_in | Positive power supply; operating range 4.5V to 5.5V per recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74HCT273DWR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
sn74hct273dwr-etched.step/sn74hct273dwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hct273dwr.step/sn74hct273dwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
be4aa8926dc70c63, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HCT273DWR
**Texas Instruments** · Flip Flops · SOIC-20-300mil
SN74HCT273DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Asynchronous clear input, active low; clears all flip-flop outputs to logic low. |
| 2 | 1Q | output | Channel 1 Q output; provides the latched logic state from the D flip-flop. |
| 3 | 1D | input | Channel 1 D input; data sampled at rising edge of CLK when CLR is high. |
| 4 | 2D | input | Channel 2 D input; data sampled at rising edge of CLK when CLR is high. |
| 5 | 2Q | output | Channel 2 Q output; provides the latched logic state from the D flip-flop. |
| 6 | 3Q | output | Channel 3 Q output; provides the latched logic state from the D flip-flop. |
| 7 | 3D | input | Channel 3 D input; data sampled at rising edge of CLK when CLR is high. |
| 8 | 4D | input | Channel 4 D input; data sampled at rising edge of CLK when CLR is high. |
| 9 | 4Q | output | Channel 4 Q output; provides the latched logic state from the D flip-flop. |
| 10 | GND | power_in | Ground; device power supply return path. |
| 11 | CLK | input | Clock input for all channels, rising edge triggered; samples all D inputs when CLR is high. |
| 12 | 5Q | output | Channel 5 Q output; provides the latched logic state from the D flip-flop. |
| 13 | 5D | input | Channel 5 D input; data sampled at rising edge of CLK when CLR is high. |
| 14 | 6D | input | Channel 6 D input; data sampled at rising edge of CLK when CLR is high. |
| 15 | 6Q | output | Channel 6 Q output; provides the latched logic state from the D flip-flop. |
| 16 | 7Q | output | Channel 7 Q output; provides the latched logic state from the D flip-flop. |
| 17 | 7D | input | Channel 7 D input; data sampled at rising edge of CLK when CLR is high. |
| 18 | 8D | input | Channel 8 D input; data sampled at rising edge of CLK when CLR is high. |
| 19 | 8Q | output | Channel 8 Q output; provides the latched logic state from the D flip-flop. |
| 20 | VCC | power_in | Positive power supply; operating range 4.5V to 5.5V per recommended operating conditions. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
## CAD (KiCad official)
- Symbol: `SN74HCT273DWR`
- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`
- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files: `sn74hct273dwr-etched.step` / `sn74hct273dwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hct273dwr.step` / `sn74hct273dwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hct273) (28 pp, sha256 `be4aa8926dc70c63`, retrieved 2026-09-23, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hct273dwr-datasheet.pdf)