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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	sn74hct244qpwrq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	9h ago
viewers	sn74hct244qpwrq1: viewers · Ray	4d ago
package.json	Publish 0.1.0 · Ray	4d ago
page.json	sn74hct244qpwrq1: annotated 3D hero (adom-hero 1.4) · Ray	9h ago
README.md	sn74hct244qpwrq1: annotated 3D hero (adom-hero 1.4) · Ray	9h ago
sn74hct244qpwrq1-etched.fit.json	sn74hct244qpwrq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	9h ago
sn74hct244qpwrq1-etched.glb	sn74hct244qpwrq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	9h ago
sn74hct244qpwrq1-etched.step	sn74hct244qpwrq1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	9h ago
sn74hct244qpwrq1-hero.glb	sn74hct244qpwrq1: annotated 3D hero (adom-hero 1.4) · Ray	9h ago
sn74hct244qpwrq1-hero.overlay.json	sn74hct244qpwrq1: annotated 3D hero (adom-hero 1.4) · Ray	9h ago
sn74hct244qpwrq1.glb	Publish 0.1.0 · Ray	4d ago
sn74hct244qpwrq1.kicad_mod	Publish 0.1.0 · Ray	4d ago
sn74hct244qpwrq1.kicad_sym	Publish 0.1.0 · Ray	4d ago
sn74hct244qpwrq1.lbr	Publish 0.1.0 · Ray	4d ago
sn74hct244qpwrq1.step	Publish 0.1.0 · Ray	4d ago

SN74HCT244QPWRQ1

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

SN74HCT244QPWRQ1 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1OE	input	Output Enable 1 input (active low), enables Y1-Y4 outputs when low and places them in high-impedance when high, TTL input compatible with VIH ≥ 2V and VIL ≤ 0.8V.
2	1A1	input	Data input A1 for buffer 1, non-inverted data passes to Y1 when 1OE is low, TTL input compatible with maximum input current II ≤ ±100nA.
3	2Y4	tri_state	Output Y4 for buffer 2, tri-state driver with ±6mA capability at 5V, output leakage current ≤ ±10µA when 2OE is high.
4	1A2	input	Data input A2 for buffer 1, non-inverted data passes to Y2 when 1OE is low, TTL input compatible with maximum input current II ≤ ±100nA.
5	2Y3	tri_state	Output Y3 for buffer 2, tri-state driver with ±6mA capability at 5V, output leakage current ≤ ±10µA when 2OE is high.
6	1A3	input	Data input A3 for buffer 1, non-inverted data passes to Y3 when 1OE is low, TTL input compatible with maximum input current II ≤ ±100nA.
7	2Y2	tri_state	Output Y2 for buffer 2, tri-state driver with ±6mA capability at 5V, output leakage current ≤ ±10µA when 2OE is high.
8	1A4	input	Data input A4 for buffer 1, non-inverted data passes to Y4 when 1OE is low, TTL input compatible with maximum input current II ≤ ±100nA.
9	2Y1	tri_state	Output Y1 for buffer 2, tri-state driver with ±6mA capability at 5V, output leakage current ≤ ±10µA when 2OE is high.
10	GND	power_in	Ground (0V reference), negative supply return for device operation.
11	2A1	input	Data input A1 for buffer 2, non-inverted data passes to Y1 when 2OE is low, TTL input compatible with maximum input current II ≤ ±100nA.
12	1Y4	tri_state	Output Y4 for buffer 1, tri-state driver with ±6mA capability at 5V, output leakage current ≤ ±10µA when 1OE is high.
13	2A2	input	Data input A2 for buffer 2, non-inverted data passes to Y2 when 2OE is low, TTL input compatible with maximum input current II ≤ ±100nA.
14	1Y3	tri_state	Output Y3 for buffer 1, tri-state driver with ±6mA capability at 5V, output leakage current ≤ ±10µA when 1OE is high.
15	2A3	input	Data input A3 for buffer 2, non-inverted data passes to Y3 when 2OE is low, TTL input compatible with maximum input current II ≤ ±100nA.
16	1Y2	tri_state	Output Y2 for buffer 1, tri-state driver with ±6mA capability at 5V, output leakage current ≤ ±10µA when 1OE is high.
17	2A4	input	Data input A4 for buffer 2, non-inverted data passes to Y4 when 2OE is low, TTL input compatible with maximum input current II ≤ ±100nA.
18	1Y1	tri_state	Output Y1 for buffer 1, tri-state driver with ±6mA capability at 5V, output leakage current ≤ ±10µA when 1OE is high.
19	2OE	input	Output Enable 2 input (active low), enables Y1-Y4 outputs when low and places them in high-impedance when high, TTL input compatible with VIH ≥ 2V and VIL ≤ 0.8V.
20	VCC	power_in	Supply voltage for device operation, recommended operating range 4.5-5.5V, requires 0.1µF bypass capacitor.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Logic
Pins	20

CAD (KiCad official)

Symbol: SN74HCT244QPWRQ1
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
Annotated 3D hero: sn74hct244qpwrq1-hero.glb (dashed pad outlines, silkscreen with pin 1, signal names; the adom-hero standard) is what the viewer shows. Downloads and EDA use the clean model, sn74hct244qpwrq1-etched.glb.
3D model files: sn74hct244qpwrq1-etched.step / sn74hct244qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hct244qpwrq1.step / sn74hct244qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (17 pp, sha256 3bffd969574117bd, retrieved 2026-10-02, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF