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SN74HCT240PWR

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74HCT240PWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

SN74HCT240PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-low output enable for buffer section 1; when high, outputs 1Y1 to 1Y4 are forced to high impedance.
2 1A1 input Data input 1A1 of buffer section 1; when 1OE is low, 1Y1 outputs the inverted value of 1A1.
3 2Y4 output Inverting 3-state output of buffer section 2; high impedance when 2OE is high.
4 1A2 input Data input 1A2 of buffer section 1; when 1OE is low, 1Y2 outputs the inverted value of 1A2.
5 2Y3 output Inverting 3-state output of buffer section 2; high impedance when 2OE is high.
6 1A3 input Data input 1A3 of buffer section 1; when 1OE is low, 1Y3 outputs the inverted value of 1A3.
7 2Y2 output Inverting 3-state output of buffer section 2; high impedance when 2OE is high.
8 1A4 input Data input 1A4 of buffer section 1; when 1OE is low, 1Y4 outputs the inverted value of 1A4.
9 2Y1 output Inverting 3-state output of buffer section 2; high impedance when 2OE is high.
10 GND power_in Ground pin.
11 2A1 input Data input 2A1 of buffer section 2; when 2OE is low, 2Y1 outputs the inverted value of 2A1.
12 1Y4 output Inverting 3-state output of buffer section 1; high impedance when 1OE is high.
13 2A2 input Data input 2A2 of buffer section 2; when 2OE is low, 2Y2 outputs the inverted value of 2A2.
14 1Y3 output Inverting 3-state output of buffer section 1; high impedance when 1OE is high.
15 2A3 input Data input 2A3 of buffer section 2; when 2OE is low, 2Y3 outputs the inverted value of 2A3.
16 1Y2 output Inverting 3-state output of buffer section 1; high impedance when 1OE is high.
17 2A4 input Data input 2A4 of buffer section 2; when 2OE is low, 2Y4 outputs the inverted value of 2A4.
18 1Y1 output Inverting 3-state output of buffer section 1; high impedance when 1OE is high.
19 2OE input Active-low output enable for buffer section 2; when high, outputs 2Y1 to 2Y4 are forced to high impedance.
20 VCC power_in Power supply pin; the recommended supply range is 4.5 V to 5.5 V (page 4).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output high voltage, IOH = -20 µA VOH 4.4 4.499 V VI = VIH or VIL, IOH = -20 µA, VCC 4.5 V 5
Output high voltage, IOH = -6 mA VOH 3.84 4.3 V VI = VIH or VIL, IOH = -6 mA, VCC 4.5 V 5
Output low voltage, IOL = 20 µA VOL 0.001 0.1 V VI = VIH or VIL, IOL = 20 µA, VCC 4.5 V 5
Output low voltage, IOL = 6 mA VOL 0.17 0.33 V VI = VIH or VIL, IOL = 6 mA, VCC 4.5 V 5
Input current II -1000 0.1 1000 nA VI = VCC or 0, VCC 5.5 V 5
Off-state (high-impedance) output current IOZ -5 0.01 5 µA VO = VCC or 0, VI = VIH or VIL, VCC 5.5 V 5
Supply current ICC 8 80 µA VI = VCC or 0, IO = 0, VCC 5.5 V 5
Supply current increase per input at TTL level ΔICC 1.4 2.9 mA One input at 0.5 V or 2.4 V, other inputs at 0 or VCC, VCC 5.5 V 5
Input capacitance Ci 3 10 pF VCC 4.5 V to 5.5 V 5
Propagation delay time, A to Y tpd 13 32 ns CL = 50 pF, VCC 4.5 V 5
Propagation delay time, A to Y tpd 12 29 ns CL = 50 pF, VCC 5.5 V 5
Enable time, OE to Y ten 21 44 ns CL = 50 pF, VCC 4.5 V 5
Enable time, OE to Y ten 19 40 ns CL = 50 pF, VCC 5.5 V 5
Disable time, OE to Y tdis 19 44 ns CL = 50 pF, VCC 4.5 V 5
Disable time, OE to Y tdis 18 40 ns CL = 50 pF, VCC 5.5 V 5
Transition time, Y tt 8 15 ns CL = 50 pF, VCC 4.5 V 5
Transition time, Y tt 7 14 ns CL = 50 pF, VCC 5.5 V 5
Propagation delay time, A to Y tpd 20 53 ns CL = 150 pF, VCC 4.5 V 5
Propagation delay time, A to Y tpd 19 48 ns CL = 150 pF, VCC 5.5 V 5
Enable time, OE to Y ten 25 65 ns CL = 150 pF, VCC 4.5 V 5
Enable time, OE to Y ten 22 59 ns CL = 150 pF, VCC 5.5 V 5
Transition time, Y tt 17 53 ns CL = 150 pF, VCC 4.5 V 5
Transition time, Y tt 14 48 ns CL = 150 pF, VCC 5.5 V 5
Supply voltage VCC 4.5 5 5.5 V 4
High-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V 4
Low-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V 4
Input voltage VI 0 V Maximum printed as VCC 4
Output voltage VO 0 V Maximum printed as VCC 4
Input transition rise/fall time Δt/Δv 500 ns 4
Operating free-air temperature TA -40 85 °C SN74HCT240 4
Supply voltage range VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -35 35 mA VO = 0 to VCC 4
Continuous current through VCC or GND -70 70 mA 4
Junction temperature TJ 150 °C 4
Storage temperature range Tstg -65 150 °C 4
Junction-to-ambient thermal resistance (PW, TSSOP) RθJA 131.8 °C/W PW (TSSOP, 20 pins) 4
Junction-to-case (top) thermal resistance (PW, TSSOP) RθJC(top) 72.2 °C/W PW (TSSOP, 20 pins) 4
Junction-to-board thermal resistance (PW, TSSOP) RθJB 82.8 °C/W PW (TSSOP, 20 pins) 4
Junction-to-top characterization parameter (PW, TSSOP) ψJT 21.5 °C/W PW (TSSOP, 20 pins) 4
Junction-to-board characterization parameter (PW, TSSOP) ψJB 82.4 °C/W PW (TSSOP, 20 pins) 4

CAD (KiCad official)

  • Symbol: SN74HCT240PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74hct240pwr-etched.step / sn74hct240pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hct240pwr.step / sn74hct240pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 9489ab61c242a8d5, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF