Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN74HCT240NSR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-20-208mil

SN74HCT240NSR from Texas Instruments, in a SOIC-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output Enable 1 input (active low); controls tri-state outputs of section 1 buffers (1Y1-1Y4).
2 1A1 input Input A1 for section 1 buffer; inverted output appears on 1Y1 when 1OE is low.
3 2Y4 tri_state Tri-state output Y4 for section 2; drives inverted version of input 2A4 when 2OE is low, otherwise high impedance.
4 1A2 input Input A2 for section 1 buffer; inverted output appears on 1Y2 when 1OE is low.
5 2Y3 tri_state Tri-state output Y3 for section 2; drives inverted version of input 2A3 when 2OE is low, otherwise high impedance.
6 1A3 input Input A3 for section 1 buffer; inverted output appears on 1Y3 when 1OE is low.
7 2Y2 tri_state Tri-state output Y2 for section 2; drives inverted version of input 2A2 when 2OE is low, otherwise high impedance.
8 1A4 input Input A4 for section 1 buffer; inverted output appears on 1Y4 when 1OE is low.
9 2Y1 tri_state Tri-state output Y1 for section 2; drives inverted version of input 2A1 when 2OE is low, otherwise high impedance.
10 GND power_in Ground reference pin.
11 2A1 input Input A1 for section 2 buffer; inverted output appears on 2Y1 when 2OE is low.
12 1Y4 tri_state Tri-state output Y4 for section 1; drives inverted version of input 1A4 when 1OE is low, otherwise high impedance.
13 2A2 input Input A2 for section 2 buffer; inverted output appears on 2Y2 when 2OE is low.
14 1Y3 tri_state Tri-state output Y3 for section 1; drives inverted version of input 1A3 when 1OE is low, otherwise high impedance.
15 2A3 input Input A3 for section 2 buffer; inverted output appears on 2Y3 when 2OE is low.
16 1Y2 tri_state Tri-state output Y2 for section 1; drives inverted version of input 1A2 when 1OE is low, otherwise high impedance.
17 2A4 input Input A4 for section 2 buffer; inverted output appears on 2Y4 when 2OE is low.
18 1Y1 tri_state Tri-state output Y1 for section 1; drives inverted version of input 1A1 when 1OE is low, otherwise high impedance.
19 2OE input Output Enable 2 input (active low); controls tri-state outputs of section 2 buffers (2Y1-2Y4).
20 VCC power_in Positive power supply pin; nominal 5V with operating range 4.5V to 5.5V per section 4.2.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-208mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74HCT240NSR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74hct240nsr-etched.step / sn74hct240nsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hct240nsr.step / sn74hct240nsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 898d3fff8f0abec6, retrieved 2026-09-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF