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SN74HCT240N
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HCT240N
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · PDIP-20
SN74HCT240N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output enable 1 (active low): when low, the first buffer bank passes inverted A data to its Y outputs; when high, those outputs are high impedance. |
| 2 | 1A1 | input | Data input 1A1 of the first buffer bank, inverted to output 1Y1 when 1OE is low. |
| 3 | 2Y4 | output | Buffer output 2Y4 from the second bank, high impedance when 2OE is high. |
| 4 | 1A2 | input | Data input 1A2 of the first buffer bank, inverted to output 1Y2 when 1OE is low. |
| 5 | 2Y3 | output | Buffer output 2Y3 from the second bank, high impedance when 2OE is high. |
| 6 | 1A3 | input | Data input 1A3 of the first buffer bank, inverted to output 1Y3 when 1OE is low. |
| 7 | 2Y2 | output | Buffer output 2Y2 from the second bank, high impedance when 2OE is high. |
| 8 | 1A4 | input | Data input 1A4 of the first buffer bank, inverted to output 1Y4 when 1OE is low. |
| 9 | 2Y1 | output | Buffer output 2Y1 from the second bank, high impedance when 2OE is high. |
| 10 | GND | power_in | Ground pin for the device. |
| 11 | 2A1 | input | Data input 2A1 of the second buffer bank, inverted to output 2Y1 when 2OE is low. |
| 12 | 1Y4 | output | Buffer output 1Y4 from the first bank, high impedance when 1OE is high. |
| 13 | 2A2 | input | Data input 2A2 of the second buffer bank, inverted to output 2Y2 when 2OE is low. |
| 14 | 1Y3 | output | Buffer output 1Y3 from the first bank, high impedance when 1OE is high. |
| 15 | 2A3 | input | Data input 2A3 of the second buffer bank, inverted to output 2Y3 when 2OE is low. |
| 16 | 1Y2 | output | Buffer output 1Y2 from the first bank, high impedance when 1OE is high. |
| 17 | 2A4 | input | Data input 2A4 of the second buffer bank, inverted to output 2Y4 when 2OE is low. |
| 18 | 1Y1 | output | Buffer output 1Y1 from the first bank, high impedance when 1OE is high. |
| 19 | 2OE | input | Output enable 2 (active low): when low, the second buffer bank passes inverted A data to its Y outputs; when high, those outputs are high impedance. |
| 20 | VCC | power_in | Supply pin; recommended operating range is 4.5 V to 5.5 V (5 V nominal), with a 0.1 µF bypass capacitor placed close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output high voltage, IOH = -20uA | VOH | 4.4 | 4.499 | V | VI = VIH or VIL, IOH = -20μA, VCC = 4.5V | 5 | |
| Output high voltage, IOH = -6mA | VOH | 3.84 | 4.3 | V | VI = VIH or VIL, IOH = -6mA, VCC = 4.5V | 5 | |
| Output low voltage, IOL = 20uA | VOL | 0.001 | 0.1 | V | VI = VIH or VIL, IOL = 20μA, VCC = 4.5V | 5 | |
| Output low voltage, IOL = 6mA | VOL | 0.17 | 0.33 | V | VI = VIH or VIL, IOL = 6mA, VCC = 4.5V | 5 | |
| Input leakage current | II | -1000 | 0.1 | 1000 | nA | VI = VCC or 0, VCC = 5.5V | 5 |
| Off-state (high-impedance) output current | IOZ | -5 | 0.01 | 5 | μA | VO = VCC or 0, VI = VIH or VIL, VCC = 5.5V | 5 |
| Quiescent supply current | ICC | 8 | 80 | μA | VI = VCC or 0, IO = 0, VCC = 5.5V | 5 | |
| Additional supply current per TTL input | ΔICC | 1.4 | 2.9 | mA | One input at 0.5V or 2.4V, other inputs at 0 or VCC, VCC = 5.5V | 5 | |
| Input capacitance | Ci | 3 | 10 | pF | VCC = 4.5V to 5.5V | 5 | |
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| High-level input voltage | VIH | 2 | V | VCC = 4.5V to 5.5V | 4 | ||
| Low-level input voltage | VIL | 0.8 | V | VCC = 4.5V to 5.5V | 4 | ||
| Input voltage | VI | 0 | V | Upper limit printed as VCC | 4 | ||
| Output voltage | VO | 0 | V | Upper limit printed as VCC | 4 | ||
| Input transition rise/fall time | Δt/Δv | 500 | ns | 4 | |||
| Operating free-air temperature (SN74HCT240) | TA | -40 | 85 | °C | Natural ventilation | 4 | |
| Supply voltage range | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VCC | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC | 4 | |
| Continuous output current | IO | -35 | 35 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -70 | 70 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature range | Tstg | -65 | 150 | °C | 4 | ||
| Propagation delay A to Y, VCC = 4.5V | tpd | 13 | 32 | ns | CL = 50pF, VCC = 4.5V | 5 | |
| Propagation delay A to Y, VCC = 5.5V | tpd | 12 | 29 | ns | CL = 50pF, VCC = 5.5V | 5 | |
| Enable time OE to Y, VCC = 4.5V | ten | 21 | 44 | ns | CL = 50pF, VCC = 4.5V | 5 | |
| Enable time OE to Y, VCC = 5.5V | ten | 19 | 40 | ns | CL = 50pF, VCC = 5.5V | 5 | |
| Disable time OE to Y, VCC = 4.5V | tdis | 19 | 44 | ns | CL = 50pF, VCC = 4.5V | 5 | |
| Disable time OE to Y, VCC = 5.5V | tdis | 18 | 40 | ns | CL = 50pF, VCC = 5.5V | 5 | |
| Output transition time Y, VCC = 4.5V | tt | 8 | 15 | ns | CL = 50pF, VCC = 4.5V | 5 | |
| Output transition time Y, VCC = 5.5V | tt | 7 | 14 | ns | CL = 50pF, VCC = 5.5V | 5 | |
| Propagation delay A to Y, VCC = 4.5V (150pF) | tpd | 20 | 53 | ns | CL = 150pF, VCC = 4.5V | 5 | |
| Propagation delay A to Y, VCC = 5.5V (150pF) | tpd | 19 | 48 | ns | CL = 150pF, VCC = 5.5V | 5 | |
| Enable time OE to Y, VCC = 4.5V (150pF) | ten | 25 | 65 | ns | CL = 150pF, VCC = 4.5V | 5 | |
| Enable time OE to Y, VCC = 5.5V (150pF) | ten | 22 | 59 | ns | CL = 150pF, VCC = 5.5V | 5 | |
| Output transition time Y, VCC = 4.5V (150pF) | tt | 17 | 53 | ns | CL = 150pF, VCC = 4.5V | 5 | |
| Output transition time Y, VCC = 5.5V (150pF) | tt | 14 | 48 | ns | CL = 150pF, VCC = 5.5V | 5 | |
| Junction-to-ambient thermal resistance (PDIP N) | RθJA | 84.6 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance (PDIP N) | RθJC(top) | 72.5 | °C/W | 4 | |||
| Junction-to-board thermal resistance (PDIP N) | RθJB | 65.3 | °C/W | 4 | |||
| Junction-to-top characterization parameter (PDIP N) | ψJT | 55.3 | °C/W | 4 | |||
| Junction-to-board characterization parameter (PDIP N) | ψJB | 65.2 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
SN74HCT240N - Footprint:
Package_DIP:DIP-20_W7.62mm - 3D model: PDIP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74hct240n-etched.step/sn74hct240n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hct240n.step/sn74hct240n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
898d3fff8f0abec6, retrieved 2026-10-15, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).