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SN74HCT138DR

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Texas Instruments Signal Switches, Multiplexers, Decoders, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs sn74hct138dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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package.json sn74hct138dr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bod… · Ray 15d ago
page.json sn74hct138dr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bod… · Ray 15d ago
README.md Initial commit: component/sn74hct138dr · Ray 1mo ago
sn74hct138dr-etched.fit.json sn74hct138dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
sn74hct138dr-etched.glb sn74hct138dr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bod… · Ray 15d ago
sn74hct138dr-etched.step sn74hct138dr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC bod… · Ray 15d ago
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sn74hct138dr.step Publish 0.1.0 · Ray 1mo ago

SN74HCT138DR

Texas Instruments · Signal Switches, Multiplexers, Decoders · SOIC-16

SN74HCT138DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Binary address select input A (LSB); TTL-compatible with VIH ≥ 2 V and VIL ≤ 0.8 V at VCC = 4.5 V to 5.5 V; selects one of eight outputs in combination with B and C.
2 B input Binary address select input B (middle bit); TTL-compatible with VIH ≥ 2 V and VIL ≤ 0.8 V at VCC = 4.5 V to 5.5 V.
3 C input Binary address select input C (MSB); TTL-compatible with VIH ≥ 2 V and VIL ≤ 0.8 V at VCC = 4.5 V to 5.5 V.
4 ~{G2A} input Active-low enable input G2A; all outputs forced high when this pin is high; must be low together with ~G2B and G1 high to enable the decoder; VIH ≥ 2 V, VIL ≤ 0.8 V, IImax = 1 µA.
5 ~{G2B} input Active-low enable input G2B; all outputs forced high when this pin is high; must be low together with ~G2A and G1 high to enable the decoder; VIH ≥ 2 V, VIL ≤ 0.8 V, IImax = 1 µA.
6 G1 input Active-high enable input; all outputs forced high when G1 is low; must be high together with ~G2A and ~G2B both low to enable the decoder; VIH ≥ 2 V, VIL ≤ 0.8 V, IImax = 1 µA.
7 Y7 output Active-low decoded output 7; asserted low when G1=H, ~G2A=L, ~G2B=L and CBA=111; VOH ≥ 3.84 V at IOH = -4 mA, VOL ≤ 0.33 V at IOL = 4 mA, tpd ≤ 45 ns at VCC = 4.5 V.
8 GND power_in Ground reference (0 V); continuous current through GND pin must not exceed ±50 mA.
9 Y6 output Active-low decoded output 6; asserted low when G1=H, ~G2A=L, ~G2B=L and CBA=110; VOH ≥ 3.84 V at IOH = -4 mA, VOL ≤ 0.33 V at IOL = 4 mA, tpd ≤ 45 ns at VCC = 4.5 V.
10 Y5 output Active-low decoded output 5; asserted low when G1=H, ~G2A=L, ~G2B=L and CBA=101; VOH ≥ 3.84 V at IOH = -4 mA, VOL ≤ 0.33 V at IOL = 4 mA, tpd ≤ 45 ns at VCC = 4.5 V.
11 Y4 output Active-low decoded output 4; asserted low when G1=H, ~G2A=L, ~G2B=L and CBA=100; VOH ≥ 3.84 V at IOH = -4 mA, VOL ≤ 0.33 V at IOL = 4 mA, tpd ≤ 45 ns at VCC = 4.5 V.
12 Y3 output Active-low decoded output 3; asserted low when G1=H, ~G2A=L, ~G2B=L and CBA=011; VOH ≥ 3.84 V at IOH = -4 mA, VOL ≤ 0.33 V at IOL = 4 mA, tpd ≤ 45 ns at VCC = 4.5 V.
13 Y2 output Active-low decoded output 2; asserted low when G1=H, ~G2A=L, ~G2B=L and CBA=010; VOH ≥ 3.84 V at IOH = -4 mA, VOL ≤ 0.33 V at IOL = 4 mA, tpd ≤ 45 ns at VCC = 4.5 V.
14 Y1 output Active-low decoded output 1; asserted low when G1=H, ~G2A=L, ~G2B=L and CBA=001; VOH ≥ 3.84 V at IOH = -4 mA, VOL ≤ 0.33 V at IOL = 4 mA, tpd ≤ 45 ns at VCC = 4.5 V.
15 Y0 output Active-low decoded output 0; asserted low when G1=H, ~G2A=L, ~G2B=L and CBA=000; VOH ≥ 3.84 V at IOH = -4 mA, VOL ≤ 0.33 V at IOL = 4 mA, tpd ≤ 45 ns at VCC = 4.5 V.
16 VCC power_in Positive supply voltage; recommended operating range 4.5 V to 5.5 V; absolute maximum 7 V; each VCC pin should be bypassed with a 0.1 µF capacitor; continuous current ±50 mA max.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74HCT138DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hct138dr-etched.step / sn74hct138dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hct138dr.step / sn74hct138dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 0d754c91dca77706, retrieved 2026-09-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (text+vision), consensus claude-opus-4-7 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF