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SN74HCT08N
Public Made by Adomby adom
Texas Instruments Logic Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HCT08N
Texas Instruments · Logic Gates · PDIP-14
SN74HCT08N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1 input A of the first 2-input AND gate; unused inputs must be tied to VCC or GND, not left floating. |
| 2 | 1B | input | Channel 1 input B of the first 2-input AND gate; unused inputs must be tied to VCC or GND, not left floating. |
| 3 | 1Y | output | Channel 1 output Y, which equals A AND B (Y = A·B, positive logic). |
| 4 | 2A | input | Channel 2 input A of the second 2-input AND gate; unused inputs must be tied to VCC or GND, not left floating. |
| 5 | 2B | input | Channel 2 input B of the second 2-input AND gate; unused inputs must be tied to VCC or GND, not left floating. |
| 6 | 2Y | output | Channel 2 output Y, which equals A AND B (Y = A·B, positive logic). |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 3Y | output | Channel 3 output Y, which equals A AND B (Y = A·B, positive logic). |
| 9 | 3A | input | Channel 3 input A of the third 2-input AND gate; unused inputs must be tied to VCC or GND, not left floating. |
| 10 | 3B | input | Channel 3 input B of the third 2-input AND gate; unused inputs must be tied to VCC or GND, not left floating. |
| 11 | 4Y | output | Channel 4 output Y, which equals A AND B (Y = A·B, positive logic). |
| 12 | 4A | input | Channel 4 input A of the fourth 2-input AND gate; unused inputs must be tied to VCC or GND, not left floating. |
| 13 | 4B | input | Channel 4 input B of the fourth 2-input AND gate; unused inputs must be tied to VCC or GND, not left floating. |
| 14 | VCC | power_in | Positive supply; recommended operating range is 4.5 V to 5.5 V (nominal 5 V), with a 0.1 µF bypass capacitor placed close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VCC | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC | 4 | |
| Continuous output current | IO | -25 | 25 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -50 | 50 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 4 | |
| High-level input voltage | VIH | 2 | V | VCC = 4.5V to 5.5V | 4 | ||
| Low-level input voltage | VIL | 0.8 | V | VCC = 4.5V to 5.5V | 4 | ||
| Input voltage | VI | 0 | V | 4 | |||
| Output voltage | VO | 0 | V | 4 | |||
| Input transition rise/fall time | Δt/Δv | 500 | ns | 4 | |||
| Operating free-air temperature | TA | -40 | 85 | °C | Natural ventilation | 4 | |
| High-level output voltage | VOH | 4.4 | 4.499 | V | VCC=4.5V; IOH=-20μA | 5 | |
| High-level output voltage | VOH | 3.84 | 4.3 | V | VCC=4.5V; IOH=-4mA | 5 | |
| Low-level output voltage | VOL | 0.001 | 0.1 | V | VCC=4.5V; IOL=20μA | 5 | |
| Low-level output voltage | VOL | 0.17 | 0.33 | V | VCC=4.5V; IOL=4mA | 5 | |
| Input hold current | II | -1000 | 0.1 | 1000 | nA | VI = VCC or 0; VCC=5.5V | 5 |
| Supply current | ICC | 2 | 20 | μA | VI = VCC or 0; IO = 0; VCC=5.5V | 5 | |
| Supply current change per input | ΔICC | 1.4 | 2.9 | mA | One input at 0.5V or 2.4V, other inputs at 0V or VCC; VCC=5.5V | 5 | |
| Input capacitance | Ci | 3 | 10 | pF | VCC = 4.5V to 5.5V | 5 | |
| Propagation delay A or B to Y | tpd | 15 | 30 | ns | CL = 50pF; VCC = 4.5V | 5 | |
| Propagation delay A or B to Y | tpd | 13 | 27 | ns | CL = 50pF; VCC = 5.5V | 5 | |
| Transition time Y | tt | 9 | 19 | ns | CL = 50pF; VCC = 4.5V | 5 | |
| Transition time Y | tt | 8 | 17 | ns | CL = 50pF; VCC = 5.5V | 5 | |
| Junction-to-ambient thermal resistance (N, PDIP) | RθJA | 103.8 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance (N, PDIP) | RθJC(top) | 91.6 | °C/W | 4 | |||
| Junction-to-board thermal resistance (N, PDIP) | RθJB | 83.5 | °C/W | 4 | |||
| Junction-to-top characterization parameter (N, PDIP) | ΨJT | 71.1 | °C/W | 4 | |||
| Junction-to-board characterization parameter (N, PDIP) | ΨJB | 83.4 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
SN74HCT08N - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74hct08n-etched.step/sn74hct08n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hct08n.step/sn74hct08n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (27 pp, sha256
dfbe03f5fff6e062, retrieved 2026-10-16, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).