component

SN74HCT02N

Public Made by Adom

by adom

Texas Instruments Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74hct02nfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN74HCT02N

Texas Instruments · Logic Gates · DIP-14

SN74HCT02N from Texas Instruments, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1Y output Gate 1 NOR output, driving up to 10 LSTTL loads with ±4 mA output drive at 5 V.
2 1A input Gate 1 input A, TTL-compatible (VIH min 2 V, VIL max 0.8 V) and must be tied to VCC or GND if unused.
3 1B input Gate 1 input B, TTL-compatible (VIH min 2 V, VIL max 0.8 V) and must be tied to VCC or GND if unused.
4 2Y output Gate 2 NOR output, driving up to 10 LSTTL loads with ±4 mA output drive at 5 V.
5 2A input Gate 2 input A, TTL-compatible (VIH min 2 V, VIL max 0.8 V) and must be tied to VCC or GND if unused.
6 2B input Gate 2 input B, TTL-compatible (VIH min 2 V, VIL max 0.8 V) and must be tied to VCC or GND if unused.
7 GND power_in Ground reference for the device.
8 3A input Gate 3 input A, TTL-compatible (VIH min 2 V, VIL max 0.8 V) and must be tied to VCC or GND if unused.
9 3B input Gate 3 input B, TTL-compatible (VIH min 2 V, VIL max 0.8 V) and must be tied to VCC or GND if unused.
10 3Y output Gate 3 NOR output, driving up to 10 LSTTL loads with ±4 mA output drive at 5 V.
11 4A input Gate 4 input A, TTL-compatible (VIH min 2 V, VIL max 0.8 V) and must be tied to VCC or GND if unused.
12 4B input Gate 4 input B, TTL-compatible (VIH min 2 V, VIL max 0.8 V) and must be tied to VCC or GND if unused.
13 4Y output Gate 4 NOR output, driving up to 10 LSTTL loads with ±4 mA output drive at 5 V.
14 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended (absolute max 7 V), with a 0.1 µF bypass capacitor recommended close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74HCT02N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74hct02n-etched.step / sn74hct02n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hct02n.step / sn74hct02n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 9d00d2ee0fb81223, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF