component

SN74HCS86PWR

Public Made by Adom

by adom

Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74hcs86pwrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

SN74HCS86PWR

Texas Instruments · Logic Gates · TSSOP-14

SN74HCS86PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Channel 1 input A of the XOR gate, a Schmitt-trigger input that tolerates slow or noisy signals.
2 1B input Channel 1 input B of the XOR gate, a Schmitt-trigger input that tolerates slow or noisy signals.
3 1Y output Channel 1 XOR output Y, which equals A XOR B in positive logic.
4 2A input Channel 2 input A of the XOR gate, a Schmitt-trigger input that tolerates slow or noisy signals.
5 2B input Channel 2 input B of the XOR gate, a Schmitt-trigger input that tolerates slow or noisy signals.
6 2Y output Channel 2 XOR output Y, which equals A XOR B in positive logic.
7 GND power_in Ground reference pin for the device.
8 3Y output Channel 3 XOR output Y, which equals A XOR B in positive logic.
9 3A input Channel 3 input A of the XOR gate, a Schmitt-trigger input that tolerates slow or noisy signals.
10 3B input Channel 3 input B of the XOR gate, a Schmitt-trigger input that tolerates slow or noisy signals.
11 4Y output Channel 4 XOR output Y, which equals A XOR B in positive logic.
12 4A input Channel 4 input A of the XOR gate, a Schmitt-trigger input that tolerates slow or noisy signals.
13 4B input Channel 4 input B of the XOR gate, a Schmitt-trigger input that tolerates slow or noisy signals.
14 VCC power_in Positive supply pin; the datasheet recommends VCC between 2 V and 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamp current IOK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Continuous output current IO -35 35 mA VO = 0 to VCC 4
Continuous current through VCC or GND -70 70 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 2 5 6 V 4
Input voltage VI 0 V 4
Output voltage VO 0 V 4
Ambient temperature TA -40 125 °C 4
Positive switching threshold VT+ 1.13 1.26 1.37 V VCC = 2V 5
Positive switching threshold VT+ 2.31 2.47 2.66 V VCC = 4.5V 5
Positive switching threshold VT+ 2.99 3.18 3.44 V VCC = 6V 5
Negative switching threshold VT- 0.55 0.62 0.71 V VCC = 2V 5
Negative switching threshold VT- 1.21 1.36 1.5 V VCC = 4.5V 5
Negative switching threshold VT- 1.56 1.79 1.99 V VCC = 6V 5
Hysteresis (positive minus negative threshold) ΔVT 0.54 0.64 0.71 V VCC = 2V 5
Hysteresis (positive minus negative threshold) ΔVT 0.94 1.11 1.27 V VCC = 4.5V 5
Hysteresis (positive minus negative threshold) ΔVT 1.2 1.38 1.57 V VCC = 6V 5
High-level output voltage VOH 4 4.3 V VI = VIH or VIL; IOH = -6mA; VCC = 4.5V 5
High-level output voltage VOH 5.4 5.75 V VI = VIH or VIL; IOH = -7.8mA; VCC = 6V 5
Low-level output voltage VOL 0.002 0.1 V VI = VIH or VIL; IOL = 20µA; VCC = 2V to 6V 5
Low-level output voltage VOL 0.18 0.3 V VI = VIH or VIL; IOL = 4mA; VCC = 4.5V 5
Low-level output voltage VOL 0.22 0.33 V VI = VIH or VIL; IOL = 7.8mA; VCC = 6V 5
Input leakage current II -1000 100 1000 nA VI = VCC or 0; VCC = 6V 5
Supply current ICC 0.1 2 µA VI = VCC or 0, IO = 0; VCC = 6V 5
Propagation delay A or B to Y tpd 15 36 ns CL = 50 pF; VCC = 2 V 6
Propagation delay A or B to Y tpd 7 13 ns CL = 50 pF; VCC = 4.5 V 6
Propagation delay A or B to Y tpd 6 12 ns CL = 50 pF; VCC = 6 V 6
Transition time Y tt 9 16 ns CL = 50 pF; VCC = 2 V 6
Transition time Y tt 5 9 ns CL = 50 pF; VCC = 4.5 V 6
Transition time Y tt 4 8 ns CL = 50 pF; VCC = 6 V 6
Junction-to-ambient thermal resistance (PW) RθJA 151.7 °C/W PW (TSSOP) 14-pin 5
Junction-to-case (top) thermal resistance (PW) RθJC(top) 79.4 °C/W PW (TSSOP) 14-pin 5
Junction-to-board thermal resistance (PW) RθJB 94.7 °C/W PW (TSSOP) 14-pin 5
Junction-to-top characterization parameter (PW) ΨJT 25.2 °C/W PW (TSSOP) 14-pin 5
Junction-to-board characterization parameter (PW) ΨJB 94.1 °C/W PW (TSSOP) 14-pin 5

CAD (KiCad official)

  • Symbol: SN74HCS86PWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74hcs86pwr-etched.step / sn74hcs86pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hcs86pwr.step / sn74hcs86pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 8f4bb222884bf20c, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF