component
SN74HCS595QPWRQ1
Public Made by Adomby adom
Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SN74HCS595QPWRQ1
Texas Instruments · Shift Registers · TSSOP-16
SN74HCS595QPWRQ1 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | output | Parallel tri-state output QB of the storage register, which goes to high impedance when OE is high. |
| 2 | QC | output | Parallel tri-state output QC of the storage register, which goes to high impedance when OE is high. |
| 3 | QD | output | Parallel tri-state output QD of the storage register, which goes to high impedance when OE is high. |
| 4 | QE | output | Parallel tri-state output QE of the storage register, which goes to high impedance when OE is high. |
| 5 | QF | output | Parallel tri-state output QF of the storage register, which goes to high impedance when OE is high. |
| 6 | QG | output | Parallel tri-state output QG of the storage register, which goes to high impedance when OE is high. |
| 7 | QH | output | Parallel tri-state output QH of the storage register, which goes to high impedance when OE is high. |
| 8 | GND | power_in | Ground reference pin for the device. |
| 9 | QH' | output | Serial output QH' that can be used for cascading to another device; it is not affected by the OE input. |
| 10 | SRCLR | input | Shift register clear input, active low, which directly overrides the shift register contents. |
| 11 | SRCLK | input | Shift register clock input, triggered on the rising edge. |
| 12 | RCLK | input | Output (storage) register clock input, triggered on the rising edge. |
| 13 | OE | input | Output enable input, active low; when high, the storage register outputs are in the high-impedance state. |
| 14 | SER | input | Serial data input to the 8-bit shift register. |
| 15 | QA | output | Parallel tri-state output QA of the storage register, which goes to high impedance when OE is high. |
| 16 | VCC | power_in | Positive supply voltage pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Continuous output current | IO | -35 | 35 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -70 | 70 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 4 | |
| Input voltage | VI | 0 | V | 4 | |||
| Output voltage | VO | 0 | V | 4 | |||
| Ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 141.2 | °C/W | PW (TSSOP) package | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 78.8 | °C/W | PW (TSSOP) package | 5 | ||
| Junction-to-board thermal resistance | RθJB | 85.8 | °C/W | PW (TSSOP) package | 5 | ||
| Positive switching threshold | VT+ | 0.7 | 1.5 | V | VCC = 2 V | 5 | |
| Positive switching threshold | VT+ | 1.7 | 3.15 | V | VCC = 4.5 V | 5 | |
| Positive switching threshold | VT+ | 2.1 | 4.2 | V | VCC = 6 V | 5 | |
| Negative switching threshold | VT- | 0.3 | 1 | V | VCC = 2 V | 5 | |
| Negative switching threshold | VT- | 0.9 | 2.2 | V | VCC = 4.5 V | 5 | |
| Negative switching threshold | VT- | 1.2 | 3 | V | VCC = 6 V | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.2 | 1 | V | VCC = 2 V | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.4 | 1.4 | V | VCC = 4.5 V | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.6 | 1.6 | V | VCC = 6 V | 5 | |
| High-level output voltage | VOH | 4 | 4.3 | V | IOH = -6 mA; VCC = 4.5 V; VI = VIH or VIL | 5 | |
| High-level output voltage | VOH | 5.4 | 5.75 | V | IOH = -7.8 mA; VCC = 6 V; VI = VIH or VIL | 5 | |
| Low-level output voltage | VOL | 0.002 | 0.1 | V | IOL = 20 µA; VCC = 2 V to 6 V; VI = VIH or VIL | 5 | |
| Low-level output voltage | VOL | 0.18 | 0.3 | V | IOL = 6 mA; VCC = 4.5 V; VI = VIH or VIL | 5 | |
| Low-level output voltage | VOL | 0.22 | 0.33 | V | IOL = 7.8 mA; VCC = 6 V; VI = VIH or VIL | 5 | |
| Input leakage current | II | -1 | 0.1 | 1 | µA | VI = VCC or 0; VCC = 6 V | 5 |
| Off-state (high-impedance state) output current | IOZ | -5 | 0.5 | 5 | µA | VO = VCC or 0; VCC = 6 V | 5 |
| Supply current | ICC | 0.1 | 2 | µA | VI = VCC or 0, IO = 0; VCC = 6 V | 5 | |
| Input capacitance | Ci | 5 | pF | VCC = 2 V to 6 V | 5 | ||
| Pulse duration SRCLK or RCLK high or low | tw | 9 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 | ||
| Pulse duration SRCLK or RCLK high or low | tw | 7 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 | ||
| Setup time SER before SRCLK↑ | tsu | 13 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 | ||
| Setup time SER before SRCLK↑ | tsu | 5 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 | ||
| Setup time SER before SRCLK↑ | tsu | 4 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 | ||
| Hold time SER after SRCLK↑ | th | 0 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 | ||
| Max switching frequency | fmax | 19 | MHz | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 | ||
| Max switching frequency | fmax | 60 | MHz | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 | ||
| Max switching frequency | fmax | 75 | MHz | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 | ||
| Propagation delay SRCLK to QH' | tpd | 28 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 | ||
| Propagation delay SRCLK to QH' | tpd | 10 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 | ||
| Propagation delay SRCLK to QH' | tpd | 9 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 | ||
| Propagation delay RCLK to QA-QH | tpd | 37 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 | ||
| Propagation delay RCLK to QA-QH | tpd | 12 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 | ||
| Propagation delay RCLK to QA-QH | tpd | 10 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 | ||
| Enable time OE to QA-QH | ten | 27 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 | ||
| Enable time OE to QA-QH | ten | 13 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 | ||
| Enable time OE to QA-QH | ten | 11 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 | ||
| Disable time OE to QA-QH | tdis | 20 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 7 | ||
| Disable time OE to QA-QH | tdis | 13 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 7 | ||
| Disable time OE to QA-QH | tdis | 12 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 7 | ||
| Transition time any output | tt | 16 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 7 | ||
| Transition time any output | tt | 9 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 7 | ||
| Transition time any output | tt | 8 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 7 |
CAD (KiCad official)
- Symbol:
SN74HCS595QPWRQ1 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74hcs595qpwrq1-etched.step/sn74hcs595qpwrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hcs595qpwrq1.step/sn74hcs595qpwrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
2956bb723ff8f093, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HCS595QPWRQ1
**Texas Instruments** · Shift Registers · TSSOP-16
SN74HCS595QPWRQ1 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | output | Parallel tri-state output QB of the storage register, which goes to high impedance when OE is high. |
| 2 | QC | output | Parallel tri-state output QC of the storage register, which goes to high impedance when OE is high. |
| 3 | QD | output | Parallel tri-state output QD of the storage register, which goes to high impedance when OE is high. |
| 4 | QE | output | Parallel tri-state output QE of the storage register, which goes to high impedance when OE is high. |
| 5 | QF | output | Parallel tri-state output QF of the storage register, which goes to high impedance when OE is high. |
| 6 | QG | output | Parallel tri-state output QG of the storage register, which goes to high impedance when OE is high. |
| 7 | QH | output | Parallel tri-state output QH of the storage register, which goes to high impedance when OE is high. |
| 8 | GND | power_in | Ground reference pin for the device. |
| 9 | QH' | output | Serial output QH' that can be used for cascading to another device; it is not affected by the OE input. |
| 10 | SRCLR | input | Shift register clear input, active low, which directly overrides the shift register contents. |
| 11 | SRCLK | input | Shift register clock input, triggered on the rising edge. |
| 12 | RCLK | input | Output (storage) register clock input, triggered on the rising edge. |
| 13 | OE | input | Output enable input, active low; when high, the storage register outputs are in the high-impedance state. |
| 14 | SER | input | Serial data input to the 8-bit shift register. |
| 15 | QA | output | Parallel tri-state output QA of the storage register, which goes to high impedance when OE is high. |
| 16 | VCC | power_in | Positive supply voltage pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | | 7 | V | | 4 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| Output clamp current | IOK | -20 | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| Continuous output current | IO | -35 | | 35 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND | | -70 | | 70 | mA | | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Supply voltage | VCC | 2 | 5 | 6 | V | | 4 |
| Input voltage | VI | 0 | | | V | | 4 |
| Output voltage | VO | 0 | | | V | | 4 |
| Ambient temperature | TA | -40 | | 125 | °C | | 4 |
| Junction-to-ambient thermal resistance | RθJA | | 141.2 | | °C/W | PW (TSSOP) package | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 78.8 | | °C/W | PW (TSSOP) package | 5 |
| Junction-to-board thermal resistance | RθJB | | 85.8 | | °C/W | PW (TSSOP) package | 5 |
| Positive switching threshold | VT+ | 0.7 | | 1.5 | V | VCC = 2 V | 5 |
| Positive switching threshold | VT+ | 1.7 | | 3.15 | V | VCC = 4.5 V | 5 |
| Positive switching threshold | VT+ | 2.1 | | 4.2 | V | VCC = 6 V | 5 |
| Negative switching threshold | VT- | 0.3 | | 1 | V | VCC = 2 V | 5 |
| Negative switching threshold | VT- | 0.9 | | 2.2 | V | VCC = 4.5 V | 5 |
| Negative switching threshold | VT- | 1.2 | | 3 | V | VCC = 6 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.2 | | 1 | V | VCC = 2 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.4 | | 1.4 | V | VCC = 4.5 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.6 | | 1.6 | V | VCC = 6 V | 5 |
| High-level output voltage | VOH | 4 | 4.3 | | V | IOH = -6 mA; VCC = 4.5 V; VI = VIH or VIL | 5 |
| High-level output voltage | VOH | 5.4 | 5.75 | | V | IOH = -7.8 mA; VCC = 6 V; VI = VIH or VIL | 5 |
| Low-level output voltage | VOL | | 0.002 | 0.1 | V | IOL = 20 µA; VCC = 2 V to 6 V; VI = VIH or VIL | 5 |
| Low-level output voltage | VOL | | 0.18 | 0.3 | V | IOL = 6 mA; VCC = 4.5 V; VI = VIH or VIL | 5 |
| Low-level output voltage | VOL | | 0.22 | 0.33 | V | IOL = 7.8 mA; VCC = 6 V; VI = VIH or VIL | 5 |
| Input leakage current | II | -1 | 0.1 | 1 | µA | VI = VCC or 0; VCC = 6 V | 5 |
| Off-state (high-impedance state) output current | IOZ | -5 | 0.5 | 5 | µA | VO = VCC or 0; VCC = 6 V | 5 |
| Supply current | ICC | | 0.1 | 2 | µA | VI = VCC or 0, IO = 0; VCC = 6 V | 5 |
| Input capacitance | Ci | | 5 | | pF | VCC = 2 V to 6 V | 5 |
| Pulse duration SRCLK or RCLK high or low | tw | 9 | | | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 |
| Pulse duration SRCLK or RCLK high or low | tw | 7 | | | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 |
| Setup time SER before SRCLK↑ | tsu | 13 | | | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 |
| Setup time SER before SRCLK↑ | tsu | 5 | | | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 |
| Setup time SER before SRCLK↑ | tsu | 4 | | | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 |
| Hold time SER after SRCLK↑ | th | 0 | | | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 |
| Max switching frequency | fmax | 19 | | | MHz | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 |
| Max switching frequency | fmax | 60 | | | MHz | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 |
| Max switching frequency | fmax | 75 | | | MHz | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 |
| Propagation delay SRCLK to QH' | tpd | | | 28 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 |
| Propagation delay SRCLK to QH' | tpd | | | 10 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 |
| Propagation delay SRCLK to QH' | tpd | | | 9 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 |
| Propagation delay RCLK to QA-QH | tpd | | | 37 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 |
| Propagation delay RCLK to QA-QH | tpd | | | 12 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 |
| Propagation delay RCLK to QA-QH | tpd | | | 10 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 |
| Enable time OE to QA-QH | ten | | | 27 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 |
| Enable time OE to QA-QH | ten | | | 13 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 |
| Enable time OE to QA-QH | ten | | | 11 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 |
| Disable time OE to QA-QH | tdis | | | 20 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 7 |
| Disable time OE to QA-QH | tdis | | | 13 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 7 |
| Disable time OE to QA-QH | tdis | | | 12 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 7 |
| Transition time any output | tt | | | 16 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 7 |
| Transition time any output | tt | | | 9 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 7 |
| Transition time any output | tt | | | 8 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 7 |
## CAD (KiCad official)
- Symbol: `SN74HCS595QPWRQ1`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `sn74hcs595qpwrq1-etched.step` / `sn74hcs595qpwrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hcs595qpwrq1.step` / `sn74hcs595qpwrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hcs595-q1) (38 pp, sha256 `2956bb723ff8f093`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hcs595qpwrq1-datasheet.pdf)