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SN74HCS595DR

Texas Instruments · Shift Registers · SOIC-16

SN74HCS595DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	QB	output	Parallel 3-state storage register output QB, forced to high impedance when OE is high.
2	QC	output	Parallel 3-state storage register output QC, forced to high impedance when OE is high.
3	QD	output	Parallel 3-state storage register output QD, forced to high impedance when OE is high.
4	QE	output	Parallel 3-state storage register output QE, forced to high impedance when OE is high.
5	QF	output	Parallel 3-state storage register output QF, forced to high impedance when OE is high.
6	QG	output	Parallel 3-state storage register output QG, forced to high impedance when OE is high.
7	QH	output	Parallel 3-state storage register output QH, forced to high impedance when OE is high.
8	GND	power_in	Ground reference pin for the device.
9	QH'	output	Serial output for cascading the shift register; its data is not affected by the operation of the OE input.
10	SRCLR	input	Shift register clear input, active low, which directly clears the shift register.
11	SRCLK	input	Shift register clock input, rising-edge triggered.
12	RCLK	input	Output (storage) register clock input, rising-edge triggered.
13	OE	input	Output enable input, active low; when it is high, the storage register outputs are placed in a high-impedance state.
14	SER	input	Serial data input to the 8-bit shift register, with Schmitt-trigger input for slow or noisy signals.
15	QA	output	Parallel 3-state storage register output QA, forced to high impedance when OE is high.
16	VCC	power_in	Positive supply; recommended operating supply voltage is 2 V to 6 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VOH High-level output voltage, IOH = -6 mA	VOH	4	4.3		V	VCC = 4.5 V; VI = VIH or VIL	5
VOH High-level output voltage, IOH = -7.8 mA	VOH	5.4	5.75		V	VCC = 6 V; VI = VIH or VIL	5
VT+ Positive switching threshold	VT+	0.7	1.5		V	VCC = 2 V	5
VT+ Positive switching threshold	VT+	1.7	3.15		V	VCC = 4.5 V	5
VT+ Positive switching threshold	VT+	2.1	4.2		V	VCC = 6 V	5
VT- Negative switching threshold	VT-	0.3	1		V	VCC = 2 V	5
VT- Negative switching threshold	VT-	0.9	2.2		V	VCC = 4.5 V	5
VT- Negative switching threshold	VT-	1.2	3		V	VCC = 6 V	5
Hysteresis (VT+ - VT-)	ΔVT	0.2	1		V	VCC = 2 V	5
Hysteresis (VT+ - VT-)	ΔVT	0.4	1.4		V	VCC = 4.5 V	5
Hysteresis (VT+ - VT-)	ΔVT	0.6	1.6		V	VCC = 6 V	5
Low-level output voltage, IOL = 6 mA	VOL		0.18	0.3	V	VCC = 4.5 V; VI = VIH or VIL	5
Low-level output voltage, IOL = 7.8 mA	VOL		0.22	0.33	V	VCC = 6 V; VI = VIH or VIL	5
Low-level output voltage, IOL = 20 uA	VOL		0.002	0.1	V	VCC = 2 V to 6 V; VI = VIH or VIL	5
Input leakage current	II		0.1	1	µA	VCC = 6 V; VI = VCC or 0	5
Off-state (high-impedance state) output current	IOZ		0.5	5	µA	VCC = 6 V; VO = VCC or 0	5
Supply current	ICC		0.1	2	µA	VCC = 6 V; VI = VCC or 0, IO = 0	5
Input capacitance	Ci		5		pF	VCC = 2 V to 6 V	5
Supply voltage	VCC	2	5	6	V		4
Input voltage	VI	0			V		4
Output voltage	VO	0			V		4
Ambient temperature	TA	-40		125	°C		4
Supply voltage	VCC	-0.5		7	V		4
Input clamp current	IIK	-20		20	mA	VI < -0.5 V or VI > VCC + 0.5 V	4
Output clamp current	IOK	-20		20	mA	VI < -0.5 V or VI > VCC + 0.5 V	4
Continuous output current	IO	-35		35	mA	VO = 0 to VCC	4
Continuous current through VCC or GND		-70		70	mA		4
Junction temperature	TJ			150	°C		4
Storage temperature	Tstg	-65		150	°C		4
Junction-to-ambient thermal resistance (D, SOIC)	RθJA		122.2		°C/W	D (SOIC) 16 pins	4
Junction-to-case (top) thermal resistance (D, SOIC)	RθJC(top)		80.9		°C/W	D (SOIC) 16 pins	4
Junction-to-board thermal resistance (D, SOIC)	RθJB		80.6		°C/W	D (SOIC) 16 pins	4
Junction-to-top characterization parameter (D, SOIC)	ΨJT		40.4		°C/W	D (SOIC) 16 pins	4
Junction-to-board characterization parameter (D, SOIC)	ΨJB		80.3		°C/W	D (SOIC) 16 pins	4

CAD (KiCad official)

Symbol: SN74HCS595DR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: sn74hcs595dr-etched.step / sn74hcs595dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hcs595dr.step / sn74hcs595dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (34 pp, sha256 04561b546ff9e2c0, retrieved 2026-10-17, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF