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SN74HCS273QPWRQ1

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Texas Instruments Logic ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74HCS273QPWRQ1

Texas Instruments · Logic ICs · TSSOP-20

SN74HCS273QPWRQ1 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low asynchronous clear shared by all eight channels.
2 1Q output Output of channel 1.
3 1D input Data input for channel 1.
4 2D input Data input for channel 2.
5 2Q output Output of channel 2.
6 3Q output Output of channel 3.
7 3D input Data input for channel 3.
8 4D input Data input for channel 4.
9 4Q output Output of channel 4.
10 GND power_in Ground reference for the device.
11 CLK input Clock shared by all channels; triggered on the rising edge.
12 5Q output Output of channel 5.
13 5D input Data input for channel 5.
14 6D input Data input for channel 6.
15 6Q output Output of channel 6.
16 7Q output Output of channel 7.
17 7D input Data input for channel 7.
18 8D input Data input for channel 8.
19 8Q output Output of channel 8.
20 VCC power_in Positive supply; the recommended operating range is 2 V to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2 6 V 4
Input voltage VI 0 V 4
Output voltage VO 0 V 4
Ambient temperature TA -40 125 °C 4
Supply voltage VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -35 35 mA VO = 0 to VCC 4
Continuous current through VCC or GND ICC -70 70 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Positive switching threshold VT+ 0.7 1.5 V VCC = 2 V 5
Positive switching threshold VT+ 1.7 3.15 V VCC = 4.5 V 5
Positive switching threshold VT+ 2.1 4.2 V VCC = 6 V 5
Negative switching threshold VT- 0.3 1 V VCC = 2 V 5
Negative switching threshold VT- 0.9 2.2 V VCC = 4.5 V 5
Negative switching threshold VT- 1.2 3 V VCC = 6 V 5
Hysteresis (VT+ - VT-) ΔVT 0.2 1 V VCC = 2 V 5
Hysteresis (VT+ - VT-) ΔVT 0.4 1.4 V VCC = 4.5 V 5
Hysteresis (VT+ - VT-) ΔVT 0.6 1.6 V VCC = 6 V 5
High-level output voltage VOH 4 4.3 V VI = VIH or VIL; IOH = -6 mA; VCC = 4.5 V 5
High-level output voltage VOH 5.4 5.75 V VI = VIH or VIL; IOH = -7.8 mA; VCC = 6 V 5
Low-level output voltage VOL 0.002 0.1 V VI = VIH or VIL; IOL = 20 µA; VCC 2 V to 6 V 5
Low-level output voltage VOL 0.18 0.3 V VI = VIH or VIL; IOL = 6 mA; VCC = 4.5 V 5
Low-level output voltage VOL 0.22 0.33 V VI = VIH or VIL; IOL = 7.8 mA; VCC = 6 V 5
Input leakage current II -1000 100 1000 nA VI = VCC or 0; VCC = 6 V 5
Supply current ICC 0.1 2 µA VI = VCC or 0; IO = 0; VCC = 6 V 5
Clock frequency fclock 49 MHz CL = 50 pF; VCC = 2 V 5
Clock frequency fclock 120 MHz CL = 50 pF; VCC = 4.5 V 5
Clock frequency fclock 135 MHz CL = 50 pF; VCC = 6 V 5
Pulse duration CLR low tw 12 ns CL = 50 pF; VCC = 2 V 5
Pulse duration CLR low tw 6 ns CL = 50 pF; VCC = 4.5 V 5
Pulse duration CLK high or low tw 12 ns CL = 50 pF; VCC = 2 V 5
Pulse duration CLK high or low tw 6 ns CL = 50 pF; VCC = 4.5 V 5
Setup time data before CLK↑ tsu 18 ns CL = 50 pF; VCC = 2 V 5
Setup time data before CLK↑ tsu 6 ns CL = 50 pF; VCC = 4.5 V 5
Setup time CLR inactive tsu 18 ns CL = 50 pF; VCC = 2 V 5
Setup time CLR inactive tsu 6 ns CL = 50 pF; VCC = 4.5 V 5
Hold time data after CLK↑ th 0 ns CL = 50 pF; VCC = 2 V 5
Disable time CLR to any Q tdis 27.3 31.2 ns CL = 50 pF; VCC = 2 V 6
Disable time CLR to any Q tdis 13.3 14.8 ns CL = 50 pF; VCC = 4.5 V 6
Disable time CLR to any Q tdis 11.7 13.2 ns CL = 50 pF; VCC = 6 V 6
Propagation delay CLK to any Q tpd 29.1 34.6 ns CL = 50 pF; VCC = 2 V 6
Propagation delay CLK to any Q tpd 13.9 16.4 ns CL = 50 pF; VCC = 4.5 V 6
Propagation delay CLK to any Q tpd 12.1 14.3 ns CL = 50 pF; VCC = 6 V 6
Junction-to-ambient thermal resistance (PW TSSOP) RθJA 134.9 °C/W PW (TSSOP) 20-pin package 4
Junction-to-case (top) thermal resistance (PW TSSOP) RθJC(top) 74.6 °C/W PW (TSSOP) 20-pin package 4
Junction-to-board thermal resistance (PW TSSOP) RθJB 86 °C/W PW (TSSOP) 20-pin package 4

CAD (KiCad official)

  • Symbol: SN74HCS273QPWRQ1
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74hcs273qpwrq1-etched.step / sn74hcs273qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hcs273qpwrq1.step / sn74hcs273qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 64e5d523105d63d2, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF