component
SN74HCS251QDRQ1
Public Made by Adomby adom
Texas Instruments Signal Switches, Multiplexers, Decoders, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74HCS251QDRQ1
Texas Instruments · Signal Switches, Multiplexers, Decoders · SOIC-16
SN74HCS251QDRQ1 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D3 | input | Data input 3, a Schmitt-trigger input that is routed to Y and W when C, B, A = L, H, H and OE is low (Table 8-1). |
| 2 | D2 | input | Data input 2, a Schmitt-trigger input that is routed to Y and W when C, B, A = L, H, L and OE is low (Table 8-1). |
| 3 | D1 | input | Data input 1, a Schmitt-trigger input that is routed to Y and W when C, B, A = L, L, H and OE is low (Table 8-1). |
| 4 | D0 | input | Data input 0, a Schmitt-trigger input that is routed to Y and W when C, B, A = L, L, L and OE is low (Table 8-1). |
| 5 | Y | tri_state | Data output (true), a balanced CMOS 3-state output that goes high impedance when OE is high. |
| 6 | W | tri_state | Data output, inverted, a balanced CMOS 3-state output that goes high impedance when OE is high. |
| 7 | OE | input | Output enable, active low; when OE is high both Y and W are disabled to the high-impedance state. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | C | input | Address select C, the most significant select bit of the 3-bit address that chooses one of D0 to D7. |
| 10 | B | input | Address select B, the middle select bit of the 3-bit address that chooses one of D0 to D7. |
| 11 | A | input | Address select A, the least significant select bit of the 3-bit address that chooses one of D0 to D7. |
| 12 | D7 | input | Data input 7, a Schmitt-trigger input that is routed to Y and W when C, B, A = H, H, H and OE is low (Table 8-1). |
| 13 | D6 | input | Data input 6, a Schmitt-trigger input that is routed to Y and W when C, B, A = H, H, L and OE is low (Table 8-1). |
| 14 | D5 | input | Data input 5, a Schmitt-trigger input that is routed to Y and W when C, B, A = H, L, H and OE is low (Table 8-1). |
| 15 | D4 | input | Data input 4, a Schmitt-trigger input that is routed to Y and W when C, B, A = H, L, L and OE is low (Table 8-1). |
| 16 | VCC | power_in | Positive supply; the recommended operating range is 2 V to 6 V, with absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Continuous output current | IO | -35 | 35 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -70 | 70 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 4 | |
| Input voltage | VI | 0 | V | 4 | |||
| Output voltage | VO | 0 | V | 4 | |||
| Ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Positive switching threshold | VT+ | 0.7 | 1.5 | V | VCC = 2 V | 5 | |
| Positive switching threshold | VT+ | 1.7 | 3.15 | V | VCC = 4.5 V | 5 | |
| Positive switching threshold | VT+ | 2.1 | 4.2 | V | VCC = 6 V | 5 | |
| Negative switching threshold | VT- | 0.3 | 1 | V | VCC = 2 V | 5 | |
| Negative switching threshold | VT- | 0.9 | 2.2 | V | VCC = 4.5 V | 5 | |
| Negative switching threshold | VT- | 1.2 | 3 | V | VCC = 6 V | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.2 | 1 | V | VCC = 2 V | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.4 | 1.4 | V | VCC = 4.5 V | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.6 | 1.6 | V | VCC = 6 V | 5 | |
| High-level output voltage | VOH | 4 | 4.3 | V | VI = VIH or VIL; IOH = -6 mA; VCC = 4.5 V | 5 | |
| High-level output voltage | VOH | 5.4 | 5.75 | V | VI = VIH or VIL; IOH = -7.8 mA; VCC = 6 V | 5 | |
| Low-level output voltage | VOL | 0.002 | 0.1 | V | VI = VIH or VIL; IOL = 20 µA; VCC = 2 V to 6 V | 5 | |
| Low-level output voltage | VOL | 0.18 | 0.3 | V | VI = VIH or VIL; IOL = 6 mA; VCC = 4.5 V | 5 | |
| Low-level output voltage | VOL | 0.22 | 0.33 | V | VI = VIH or VIL; IOL = 7.8 mA; VCC = 6 V | 5 | |
| Input leakage current | II | -1 | 0.1 | 1 | µA | VI = VCC or 0; VCC = 6 V | 5 |
| Off-state (high-impedance state) output current | IOZ | -0.5 | 0.5 | µA | VO = VCC or 0; VCC = 6 V | 5 | |
| Supply current | ICC | 0.1 | 2 | µA | VI = VCC or 0, IO = 0; VCC = 6 V | 5 | |
| Max switching frequency (-40°C to 125°C min) | fmax | 5 | MHz | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 5 | ||
| Max switching frequency (-40°C to 125°C min) | fmax | 25 | MHz | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 5 | ||
| Max switching frequency (-40°C to 125°C min) | fmax | 29 | MHz | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 5 | ||
| Propagation delay A, B, or C to W or Y (-40°C to 125°C max) | tpd | 72 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 5 | ||
| Propagation delay A, B, or C to W or Y (-40°C to 125°C max) | tpd | 26 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 5 | ||
| Propagation delay A, B, or C to W or Y (-40°C to 125°C max) | tpd | 22 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 5 | ||
| Propagation delay D to W or Y (-40°C to 125°C max) | tpd | 70 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 5 | ||
| Propagation delay D to W or Y (-40°C to 125°C max) | tpd | 26 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 5 | ||
| Propagation delay D to W or Y (-40°C to 125°C max) | tpd | 22 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 5 | ||
| Enable time OE to W or Y (-40°C to 125°C max) | ten | 44 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 5 | ||
| Enable time OE to W or Y (-40°C to 125°C max) | ten | 20 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 5 | ||
| Enable time OE to W or Y (-40°C to 125°C max) | ten | 16 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 5 | ||
| Disable time OE to W or Y (-40°C to 125°C max) | tdis | 32 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 5 | ||
| Disable time OE to W or Y (-40°C to 125°C max) | tdis | 20 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 5 | ||
| Disable time OE to W or Y (-40°C to 125°C max) | tdis | 18 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 5 | ||
| Transition time W or Y (-40°C to 125°C max) | tt | 16 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 | ||
| Transition time W or Y (-40°C to 125°C max) | tt | 9 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 | ||
| Transition time W or Y (-40°C to 125°C max) | tt | 8 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 | ||
| Transition time any output (-40°C to 125°C max) | tt | 75 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 | ||
| Transition time any output (-40°C to 125°C max) | tt | 15 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 | ||
| Transition time any output (-40°C to 125°C max) | tt | 13 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 | ||
| Junction-to-ambient thermal resistance (D, SOIC-16) | RθJA | 122.2 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance (D, SOIC-16) | RθJC(top) | 80.9 | °C/W | 4 | |||
| Junction-to-board thermal resistance (D, SOIC-16) | RθJB | 80.6 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
SN74HCS251QDRQ1 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
sn74hcs251qdrq1-etched.step/sn74hcs251qdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hcs251qdrq1.step/sn74hcs251qdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
73467702117190ce, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HCS251QDRQ1
**Texas Instruments** · Signal Switches, Multiplexers, Decoders · SOIC-16
SN74HCS251QDRQ1 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D3 | input | Data input 3, a Schmitt-trigger input that is routed to Y and W when C, B, A = L, H, H and OE is low (Table 8-1). |
| 2 | D2 | input | Data input 2, a Schmitt-trigger input that is routed to Y and W when C, B, A = L, H, L and OE is low (Table 8-1). |
| 3 | D1 | input | Data input 1, a Schmitt-trigger input that is routed to Y and W when C, B, A = L, L, H and OE is low (Table 8-1). |
| 4 | D0 | input | Data input 0, a Schmitt-trigger input that is routed to Y and W when C, B, A = L, L, L and OE is low (Table 8-1). |
| 5 | Y | tri_state | Data output (true), a balanced CMOS 3-state output that goes high impedance when OE is high. |
| 6 | W | tri_state | Data output, inverted, a balanced CMOS 3-state output that goes high impedance when OE is high. |
| 7 | OE | input | Output enable, active low; when OE is high both Y and W are disabled to the high-impedance state. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | C | input | Address select C, the most significant select bit of the 3-bit address that chooses one of D0 to D7. |
| 10 | B | input | Address select B, the middle select bit of the 3-bit address that chooses one of D0 to D7. |
| 11 | A | input | Address select A, the least significant select bit of the 3-bit address that chooses one of D0 to D7. |
| 12 | D7 | input | Data input 7, a Schmitt-trigger input that is routed to Y and W when C, B, A = H, H, H and OE is low (Table 8-1). |
| 13 | D6 | input | Data input 6, a Schmitt-trigger input that is routed to Y and W when C, B, A = H, H, L and OE is low (Table 8-1). |
| 14 | D5 | input | Data input 5, a Schmitt-trigger input that is routed to Y and W when C, B, A = H, L, H and OE is low (Table 8-1). |
| 15 | D4 | input | Data input 4, a Schmitt-trigger input that is routed to Y and W when C, B, A = H, L, L and OE is low (Table 8-1). |
| 16 | VCC | power_in | Positive supply; the recommended operating range is 2 V to 6 V, with absolute maximum 7 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | | 7 | V | | 4 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| Output clamp current | IOK | -20 | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| Continuous output current | IO | -35 | | 35 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND | | -70 | | 70 | mA | | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Supply voltage | VCC | 2 | 5 | 6 | V | | 4 |
| Input voltage | VI | 0 | | | V | | 4 |
| Output voltage | VO | 0 | | | V | | 4 |
| Ambient temperature | TA | -40 | | 125 | °C | | 4 |
| Positive switching threshold | VT+ | 0.7 | | 1.5 | V | VCC = 2 V | 5 |
| Positive switching threshold | VT+ | 1.7 | | 3.15 | V | VCC = 4.5 V | 5 |
| Positive switching threshold | VT+ | 2.1 | | 4.2 | V | VCC = 6 V | 5 |
| Negative switching threshold | VT- | 0.3 | | 1 | V | VCC = 2 V | 5 |
| Negative switching threshold | VT- | 0.9 | | 2.2 | V | VCC = 4.5 V | 5 |
| Negative switching threshold | VT- | 1.2 | | 3 | V | VCC = 6 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.2 | | 1 | V | VCC = 2 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.4 | | 1.4 | V | VCC = 4.5 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.6 | | 1.6 | V | VCC = 6 V | 5 |
| High-level output voltage | VOH | 4 | 4.3 | | V | VI = VIH or VIL; IOH = -6 mA; VCC = 4.5 V | 5 |
| High-level output voltage | VOH | 5.4 | 5.75 | | V | VI = VIH or VIL; IOH = -7.8 mA; VCC = 6 V | 5 |
| Low-level output voltage | VOL | | 0.002 | 0.1 | V | VI = VIH or VIL; IOL = 20 µA; VCC = 2 V to 6 V | 5 |
| Low-level output voltage | VOL | | 0.18 | 0.3 | V | VI = VIH or VIL; IOL = 6 mA; VCC = 4.5 V | 5 |
| Low-level output voltage | VOL | | 0.22 | 0.33 | V | VI = VIH or VIL; IOL = 7.8 mA; VCC = 6 V | 5 |
| Input leakage current | II | -1 | 0.1 | 1 | µA | VI = VCC or 0; VCC = 6 V | 5 |
| Off-state (high-impedance state) output current | IOZ | -0.5 | | 0.5 | µA | VO = VCC or 0; VCC = 6 V | 5 |
| Supply current | ICC | | 0.1 | 2 | µA | VI = VCC or 0, IO = 0; VCC = 6 V | 5 |
| Max switching frequency (-40°C to 125°C min) | fmax | 5 | | | MHz | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 5 |
| Max switching frequency (-40°C to 125°C min) | fmax | 25 | | | MHz | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 5 |
| Max switching frequency (-40°C to 125°C min) | fmax | 29 | | | MHz | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 5 |
| Propagation delay A, B, or C to W or Y (-40°C to 125°C max) | tpd | | | 72 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 5 |
| Propagation delay A, B, or C to W or Y (-40°C to 125°C max) | tpd | | | 26 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 5 |
| Propagation delay A, B, or C to W or Y (-40°C to 125°C max) | tpd | | | 22 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 5 |
| Propagation delay D to W or Y (-40°C to 125°C max) | tpd | | | 70 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 5 |
| Propagation delay D to W or Y (-40°C to 125°C max) | tpd | | | 26 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 5 |
| Propagation delay D to W or Y (-40°C to 125°C max) | tpd | | | 22 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 5 |
| Enable time OE to W or Y (-40°C to 125°C max) | ten | | | 44 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 5 |
| Enable time OE to W or Y (-40°C to 125°C max) | ten | | | 20 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 5 |
| Enable time OE to W or Y (-40°C to 125°C max) | ten | | | 16 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 5 |
| Disable time OE to W or Y (-40°C to 125°C max) | tdis | | | 32 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 5 |
| Disable time OE to W or Y (-40°C to 125°C max) | tdis | | | 20 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 5 |
| Disable time OE to W or Y (-40°C to 125°C max) | tdis | | | 18 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 5 |
| Transition time W or Y (-40°C to 125°C max) | tt | | | 16 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 |
| Transition time W or Y (-40°C to 125°C max) | tt | | | 9 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 |
| Transition time W or Y (-40°C to 125°C max) | tt | | | 8 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 |
| Transition time any output (-40°C to 125°C max) | tt | | | 75 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V | 6 |
| Transition time any output (-40°C to 125°C max) | tt | | | 15 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V | 6 |
| Transition time any output (-40°C to 125°C max) | tt | | | 13 | ns | CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V | 6 |
| Junction-to-ambient thermal resistance (D, SOIC-16) | RθJA | | 122.2 | | °C/W | | 4 |
| Junction-to-case (top) thermal resistance (D, SOIC-16) | RθJC(top) | | 80.9 | | °C/W | | 4 |
| Junction-to-board thermal resistance (D, SOIC-16) | RθJB | | 80.6 | | °C/W | | 4 |
## CAD (KiCad official)
- Symbol: `SN74HCS251QDRQ1`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `sn74hcs251qdrq1-etched.step` / `sn74hcs251qdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hcs251qdrq1.step` / `sn74hcs251qdrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hcs251-q1) (26 pp, sha256 `73467702117190ce`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hcs251qdrq1-datasheet.pdf)