component

SN74HCS20QPWRQ1

Public Made by Adom

by adom

Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74hcs20qpwrq1factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
sn74hcs20qpwrq1 / README.md
History Download
Ray Publish 0.1.0 62e1f74 8d ago

SN74HCS20QPWRQ1

Texas Instruments · Logic Gates · TSSOP-14

SN74HCS20QPWRQ1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Channel 1 input A of the 4-input NAND gate with Schmitt-trigger inputs; unused inputs must be tied to VCC or GND, not left floating.
2 1B input Channel 1 input B of the 4-input NAND gate with Schmitt-trigger inputs; unused inputs must be tied to VCC or GND, not left floating.
3 NC unconnected Not internally connected.
4 1C input Channel 1 input C of the 4-input NAND gate with Schmitt-trigger inputs; unused inputs must be tied to VCC or GND, not left floating.
5 1D input Channel 1 input D of the 4-input NAND gate with Schmitt-trigger inputs; unused inputs must be tied to VCC or GND, not left floating.
6 1Y output Channel 1 output Y = A·B·C·D from a balanced CMOS push-pull output; avoid overcurrent beyond the Absolute Maximum Ratings.
7 GND power_in Ground reference for the device.
8 2Y output Channel 2 output Y = A·B·C·D from a balanced CMOS push-pull output; avoid overcurrent beyond the Absolute Maximum Ratings.
9 2A input Channel 2 input A of the 4-input NAND gate with Schmitt-trigger inputs; unused inputs must be tied to VCC or GND, not left floating.
10 2B input Channel 2 input B of the 4-input NAND gate with Schmitt-trigger inputs; unused inputs must be tied to VCC or GND, not left floating.
11 NC unconnected Not internally connected.
12 2C input Channel 2 input C of the 4-input NAND gate with Schmitt-trigger inputs; unused inputs must be tied to VCC or GND, not left floating.
13 2D input Channel 2 input D of the 4-input NAND gate with Schmitt-trigger inputs; unused inputs must be tied to VCC or GND, not left floating.
14 VCC power_in Positive supply; recommended operating range is 2 V to 6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < -0.5 or VI > VCC + 0.5 4
Output clamp current IOK -20 20 mA VO < -0.5 or VO > VCC + 0.5 4
Continuous output current IO -35 35 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 2 6 V 4
Input voltage VI 0 V 4
Output voltage VO 0 V 4
Ambient temperature TA -40 125 °C 4
Positive switching threshold VT+ 0.7 1.5 V VCC = 2 V 5
Positive switching threshold VT+ 1.7 3.15 V VCC = 4.5 V 5
Positive switching threshold VT+ 2.1 4.2 V VCC = 6 V 5
Negative switching threshold VT- 0.3 1 V VCC = 2 V 5
Negative switching threshold VT- 0.9 2.2 V VCC = 4.5 V 5
Negative switching threshold VT- 1.2 3 V VCC = 6 V 5
Hysteresis (VT+ - VT-) ΔVT 0.2 1 V VCC = 2 V 5
Hysteresis (VT+ - VT-) ΔVT 0.4 1.4 V VCC = 4.5 V 5
Hysteresis (VT+ - VT-) ΔVT 0.6 1.6 V VCC = 6 V 5
High-level output voltage VOH 4 4.3 V VI = VIH or VIL; IOH = -6 mA; VCC = 4.5 V 5
High-level output voltage VOH 5.4 5.75 V VI = VIH or VIL; IOH = -7.8 mA; VCC = 6 V 5
Low-level output voltage VOL 0.002 0.1 V VI = VIH or VIL; IOL = 20 µA; VCC = 2 V to 6 V 5
Low-level output voltage VOL 0.18 0.3 V VI = VIH or VIL; IOL = 6 mA; VCC = 4.5 V 5
Low-level output voltage VOL 0.22 0.33 V VI = VIH or VIL; IOL = 7.8 mA; VCC = 6 V 5
Input leakage current II -1000 100 1000 nA VI = VCC or 0; VCC = 6 V 5
Supply current ICC 0.1 2 µA VI = VCC or 0, IO = 0; VCC = 6 V 5
Propagation delay (A or B to Y) tpd 19 56 ns VCC = 2 V 5
Propagation delay (A or B to Y) tpd 8 22 ns VCC = 4.5 V 5
Propagation delay (A or B to Y) tpd 7 19 ns VCC = 6 V 5
Transition-time (Y) tt 9 17 ns VCC = 2 V 5
Transition-time (Y) tt 5 8 ns VCC = 4.5 V 5
Transition-time (Y) tt 4 7 ns VCC = 6 V 5
Junction-to-ambient thermal resistance RθJA 151.7 °C/W PW (TSSOP) 14-pin package 4
Junction-to-case (top) thermal resistance RθJC(top) 79.4 °C/W PW (TSSOP) 14-pin package 4
Junction-to-board thermal resistance RθJB 94.7 °C/W PW (TSSOP) 14-pin package 4
Junction-to-top characterization parameter ΨJT 25.2 °C/W PW (TSSOP) 14-pin package 4
Junction-to-board characterization parameter ΨJB 94.1 °C/W PW (TSSOP) 14-pin package 4

CAD (KiCad official)

  • Symbol: SN74HCS20QPWRQ1
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74hcs20qpwrq1-etched.step / sn74hcs20qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hcs20qpwrq1.step / sn74hcs20qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 67b533f52c9a3d20, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF