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SN74HCS20DR

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Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74HCS20DR

Texas Instruments · Logic Gates · SOIC-14

SN74HCS20DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Channel 1, input A of the first 4-input NAND gate.
2 1B input Channel 1, input B of the first 4-input NAND gate.
3 NC unconnected Not internally connected; leave unconnected.
4 1C input Channel 1, input C of the first 4-input NAND gate.
5 1D input Channel 1, input D of the first 4-input NAND gate.
6 1Y output Channel 1, output Y of the first NAND gate.
7 GND power_in Ground reference for the device.
8 2Y output Channel 2, output Y of the second NAND gate.
9 2A input Channel 2, input A of the second 4-input NAND gate.
10 2B input Channel 2, input B of the second 4-input NAND gate.
11 NC unconnected Not internally connected; leave unconnected.
12 2C input Channel 2, input C of the second 4-input NAND gate.
13 2D input Channel 2, input D of the second 4-input NAND gate.
14 VCC power_in Positive supply pin for the device.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (recommended) VCC 2 6 V 4
Input voltage (recommended) VI 0 V 4
Output voltage (recommended) VO 0 V 4
Ambient temperature (recommended) TA -40 125 °C 4
Supply voltage (absolute maximum) VCC -0.5 7 V 4
Input clamp current (absolute maximum) IIK -20 20 mA VI < -0.5 or VI > VCC + 0.5 4
Output clamp current (absolute maximum) IOK -20 20 mA VO < -0.5 or VO > VCC + 0.5 4
Continuous output current (absolute maximum) IO -35 35 mA VO = 0 to VCC 4
Continuous current through VCC or GND (absolute maximum) -70 70 mA 4
Junction temperature (absolute maximum) TJ 150 °C 4
Storage temperature (absolute maximum) Tstg -65 150 °C 4
Positive switching threshold VT+ (VCC 2 V) VT+ 1.13 1.26 1.37 V 5
Positive switching threshold VT+ (VCC 4.5 V) VT+ 2.31 2.47 2.66 V 5
Positive switching threshold VT+ (VCC 6 V) VT+ 2.99 3.18 3.44 V 5
Negative switching threshold VT- (VCC 2 V) VT- 0.55 0.62 0.71 V 5
Negative switching threshold VT- (VCC 4.5 V) VT- 1.21 1.36 1.5 V 5
Negative switching threshold VT- (VCC 6 V) VT- 1.56 1.79 1.99 V 5
Hysteresis ΔVT (VCC 2 V) ΔVT 0.54 0.64 0.71 V 5
Hysteresis ΔVT (VCC 4.5 V) ΔVT 0.94 1.11 1.27 V 5
Hysteresis ΔVT (VCC 6 V) ΔVT 1.2 1.38 1.57 V 5
High-level output voltage VOH (VCC 4.5 V) VOH 4 4.3 V VI = VIH or VIL, IOH = -6mA 5
High-level output voltage VOH (VCC 6 V) VOH 5.4 5.75 V VI = VIH or VIL, IOH = -7.8mA 5
Low-level output voltage VOL (VCC 2 V to 6 V) VOL 0.002 0.1 V VI = VIH or VIL, IOL = 20µA 5
Low-level output voltage VOL (VCC 4.5 V) VOL 0.18 0.3 V VI = VIH or VIL, IOL = 4mA 5
Low-level output voltage VOL (VCC 6 V) VOL 0.22 0.33 V VI = VIH or VIL, IOL = 7.8mA 5
Input leakage current (± magnitude, VCC 6 V) II 100 1000 nA VI = VCC or 0, VCC 6V 5
Supply current (VCC 6 V) ICC 0.1 2 µA VI = VCC or 0, IO = 0 5
Propagation delay tpd (VCC 2 V) tpd 19 56 ns A or B to Y 5
Propagation delay tpd (VCC 4.5 V) tpd 8 22 ns A or B to Y 5
Propagation delay tpd (VCC 6 V) tpd 7 19 ns A or B to Y 5
Transition time tt (VCC 2 V) tt 9 17 ns to Y 5
Transition time tt (VCC 4.5 V) tt 5 8 ns to Y 5
Transition time tt (VCC 6 V) tt 4 7 ns to Y 5
Junction-to-ambient thermal resistance RθJA (D, SOIC) RθJA 133.6 °C/W 4
Junction-to-case (top) thermal resistance RθJC(top) (D, SOIC) RθJC(top) 89 °C/W 4
Junction-to-board thermal resistance RθJB (D, SOIC) RθJB 89.5 °C/W 4
Junction-to-top characterization parameter ΨJT (D, SOIC) ΨJT 45.5 °C/W 4
Junction-to-board characterization parameter ΨJB (D, SOIC) ΨJB 89.1 °C/W 4

CAD (KiCad official)

  • Symbol: SN74HCS20DR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74hcs20dr-etched.step / sn74hcs20dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hcs20dr.step / sn74hcs20dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 bf599281c02857e8, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF