# SN74HCS174QDRQ1

**Texas Instruments** · Flip Flops · SOIC-16

SN74HCS174QDRQ1 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Active-low clear input that resets all six flip-flop outputs low; Schmitt-trigger input. |
| 2 | 1Q | output | Channel 1 Q output, balanced CMOS push-pull with ±7.8 mA drive at 6 V. |
| 3 | 1D | input | Channel 1 D data input, Schmitt-trigger, sampled on rising CLK edge. |
| 4 | 2D | input | Channel 2 D data input, Schmitt-trigger, sampled on rising CLK edge. |
| 5 | 2Q | output | Channel 2 Q output, balanced CMOS push-pull with ±7.8 mA drive at 6 V. |
| 6 | 3D | input | Channel 3 D data input, Schmitt-trigger, sampled on rising CLK edge. |
| 7 | 3Q | output | Channel 3 Q output, balanced CMOS push-pull with ±7.8 mA drive at 6 V. |
| 8 | GND | power_in | Ground; continuous current through GND is limited to ±70 mA. |
| 9 | CLK | input | Shared clock input for all channels, rising-edge triggered, Schmitt-trigger. |
| 10 | 4Q | output | Channel 4 Q output, balanced CMOS push-pull with ±7.8 mA drive at 6 V. |
| 11 | 4D | input | Channel 4 D data input, Schmitt-trigger, sampled on rising CLK edge. |
| 12 | 5Q | output | Channel 5 Q output, balanced CMOS push-pull with ±7.8 mA drive at 6 V. |
| 13 | 5D | input | Channel 5 D data input, Schmitt-trigger, sampled on rising CLK edge. |
| 14 | 6D | input | Channel 6 D data input, Schmitt-trigger, sampled on rising CLK edge. |
| 15 | 6Q | output | Channel 6 Q output, balanced CMOS push-pull with ±7.8 mA drive at 6 V. |
| 16 | VCC | power_in | Positive supply, 2 V to 6 V recommended operating range; a 0.1-µF bypass capacitor is recommended. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic ICs |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (abs max) | VCC | -0.5 |  | 7 | V |  | 4 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| Output clamp current | IOK | -20 |  | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| Continuous output current | IO | -35 |  | 35 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND |  | -70 |  | 70 | mA |  | 4 |
| Junction temperature | TJ |  |  | 150 | °C | Guaranteed by design | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| ESD HBM | V(ESD) | -4000 |  | 4000 | V | HBM per AEC Q100-002, Classification Level 2 | 4 |
| ESD CDM | V(ESD) | -1500 |  | 1500 | V | CDM per AEC Q100-011, Classification Level C6 | 4 |
| Supply voltage | VCC | 2 | 5 | 6 | V |  | 4 |
| Input voltage | VI | 0 |  | 6 | V | 0 to VCC | 4 |
| Output voltage | VO | 0 |  | 6 | V | 0 to VCC | 4 |
| Ambient temperature | TA | -40 |  | 125 | °C |  | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 122.2 |  | °C/W | D (SOIC) 16 pins | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 80.9 |  | °C/W | D (SOIC) 16 pins | 4 |
| Junction-to-board thermal resistance | RθJB |  | 80.6 |  | °C/W | D (SOIC) 16 pins | 4 |
| Junction-to-top characterization parameter | ΨJT |  | 40.4 |  | °C/W | D (SOIC) 16 pins | 4 |
| Junction-to-board characterization parameter | ΨJB |  | 80.3 |  | °C/W | D (SOIC) 16 pins | 4 |
| Positive switching threshold | VT+ | 0.7 |  | 1.5 | V | VCC = 2 V | 5 |
| Positive switching threshold | VT+ | 1.7 |  | 3.15 | V | VCC = 4.5 V | 5 |
| Positive switching threshold | VT+ | 2.1 |  | 4.2 | V | VCC = 6 V | 5 |
| Negative switching threshold | VT- | 0.3 |  | 1 | V | VCC = 2 V | 5 |
| Negative switching threshold | VT- | 0.9 |  | 2.2 | V | VCC = 4.5 V | 5 |
| Negative switching threshold | VT- | 1.2 |  | 3 | V | VCC = 6 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.2 |  | 1 | V | VCC = 2 V; guaranteed by design | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.4 |  | 1.4 | V | VCC = 4.5 V; guaranteed by design | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.6 |  | 1.6 | V | VCC = 6 V; guaranteed by design | 5 |
| High-level output voltage | VOH | 4 | 4.3 |  | V | VI = VIH or VIL, IOH = -6 mA, VCC = 4.5 V | 5 |
| High-level output voltage | VOH | 5.4 | 5.75 |  | V | VI = VIH or VIL, IOH = -7.8 mA, VCC = 6 V | 5 |
| Low-level output voltage | VOL |  | 0.002 | 0.1 | V | VI = VIH or VIL, IOL = 20 µA, VCC = 2 V to 6 V | 5 |
| Low-level output voltage | VOL |  | 0.18 | 0.3 | V | VI = VIH or VIL, IOL = 6 mA, VCC = 4.5 V | 5 |
| Low-level output voltage | VOL |  | 0.22 | 0.33 | V | VI = VIH or VIL, IOL = 7.8 mA, VCC = 6 V | 5 |
| Input leakage current | II | -1000 | 100 | 1000 | nA | VI = VCC or 0, VCC = 6 V | 5 |
| Supply current | ICC |  | 0.1 | 2 | µA | VI = VCC or 0, IO = 0, VCC = 6 V | 5 |
| Input capacitance | Ci |  | 5 |  | pF | VCC = 2 V to 6 V | 5 |
| Clock frequency | fclock | 40 |  |  | MHz | VCC = 2 V, TA = -40°C to 125°C, CL = 50 pF | 5 |
| Clock frequency | fclock | 130 |  |  | MHz | VCC = 4.5 V, TA = -40°C to 125°C, CL = 50 pF | 5 |
| Clock frequency | fclock | 145 |  |  | MHz | VCC = 6 V, TA = -40°C to 125°C, CL = 50 pF | 5 |
| Pulse duration, CLR low | tw | 12 |  |  | ns | VCC = 2 V, TA = -40°C to 125°C | 5 |
| Pulse duration, CLR low | tw | 6 |  |  | ns | VCC = 4.5 V, TA = -40°C to 125°C | 5 |
| Pulse duration, CLK high or low | tw | 12 |  |  | ns | VCC = 2 V, TA = -40°C to 125°C | 5 |
| Pulse duration, CLK high or low | tw | 6 |  |  | ns | VCC = 4.5 V, TA = -40°C to 125°C | 5 |
| Setup time, data | tsu | 18 |  |  | ns | VCC = 2 V, TA = -40°C to 125°C | 5 |
| Setup time, data | tsu | 6 |  |  | ns | VCC = 4.5 V, TA = -40°C to 125°C | 5 |
| Setup time, CLR inactive | tsu | 18 |  |  | ns | VCC = 2 V, TA = -40°C to 125°C | 5 |
| Setup time, CLR inactive | tsu | 6 |  |  | ns | VCC = 4.5 V, TA = -40°C to 125°C | 5 |
| Propagation delay, CLK to any output | tpd |  |  | 35 | ns | VCC = 2 V, TA = -40°C to 125°C, CL = 50 pF | 6 |
| Propagation delay, CLK to any output | tpd |  |  | 18 | ns | VCC = 4.5 V, TA = -40°C to 125°C, CL = 50 pF | 6 |
| Propagation delay, CLK to any output | tpd |  |  | 16 | ns | VCC = 6 V, TA = -40°C to 125°C, CL = 50 pF | 6 |
| Propagation delay, CLR to any output | tpd |  |  | 35 | ns | VCC = 2 V, TA = -40°C to 125°C, CL = 50 pF | 6 |
| Propagation delay, CLR to any output | tpd |  |  | 18 | ns | VCC = 4.5 V, TA = -40°C to 125°C, CL = 50 pF | 6 |
| Propagation delay, CLR to any output | tpd |  |  | 16 | ns | VCC = 6 V, TA = -40°C to 125°C, CL = 50 pF | 6 |
| Power dissipation capacitance per gate | Cpd |  | 10 |  | pF | No load, VCC = 2 V to 6 V | 6 |

## CAD (KiCad official)

- Symbol: `SN74HCS174QDRQ1`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `sn74hcs174qdrq1-etched.step` / `sn74hcs174qdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hcs174qdrq1.step` / `sn74hcs174qdrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hcs174-q1) (25 pp, sha256 `25412ef19e46b7b7`, retrieved 2026-10-22, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74hcs174qdrq1-datasheet.pdf)