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SN74HCS166PWR
Public Made by Adomby adom
Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74HCS166PWR
Texas Instruments · Shift Registers · TSSOP-16
SN74HCS166PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SER | input | Serial input to the 8-bit shift register. |
| 2 | A | input | Parallel data input A for parallel loading when SH/LD is low. |
| 3 | B | input | Parallel data input B for parallel loading when SH/LD is low. |
| 4 | C | input | Parallel data input C for parallel loading when SH/LD is low. |
| 5 | D | input | Parallel data input D for parallel loading when SH/LD is low. |
| 6 | CLK INH | input | Clock inhibit input that controls whether the clock is enabled. |
| 7 | CLK | input | Clock input, positive edge triggered. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | CLR | input | Clear input, active low. |
| 10 | E | input | Parallel data input E for parallel loading when SH/LD is low. |
| 11 | F | input | Parallel data input F for parallel loading when SH/LD is low. |
| 12 | G | input | Parallel data input G for parallel loading when SH/LD is low. |
| 13 | QH | output | QH serial output of the shift register. |
| 14 | H | input | Parallel data input H for parallel loading when SH/LD is low. |
| 15 | SH/LD | input | Shift/load input: enables shifting when high and loads parallel data when low. |
| 16 | VCC | power_in | Positive supply; recommended supply voltage range is 2 V to 6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2 | 5 | 6 | V | Recommended operating conditions, free-air temperature range | 4 |
| Input voltage | VI | 0 | V | Maximum is VCC | 4 | ||
| Output voltage | VO | 0 | V | Maximum is VCC | 4 | ||
| Ambient temperature | TA | -40 | 125 | °C | Operating free-air temperature range | 4 | |
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Continuous output current | IO | -35 | 35 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -70 | 70 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance (PW TSSOP) | RθJA | 141.2 | °C/W | PW (TSSOP) 16 pins | 4 | ||
| Junction-to-case (top) thermal resistance (PW TSSOP) | RθJC(top) | 78.8 | °C/W | PW (TSSOP) 16 pins | 4 | ||
| Junction-to-board thermal resistance (PW TSSOP) | RθJB | 85.8 | °C/W | PW (TSSOP) 16 pins | 4 | ||
| Positive switching threshold | VT+ | 0.7 | 1.5 | V | VCC = 2 V | 5 | |
| Positive switching threshold | VT+ | 1.7 | 3.15 | V | VCC = 4.5 V | 5 | |
| Positive switching threshold | VT+ | 2.1 | 4.2 | V | VCC = 6 V | 5 | |
| Negative switching threshold | VT- | 0.3 | 1 | V | VCC = 2 V | 5 | |
| Negative switching threshold | VT- | 0.9 | 2.2 | V | VCC = 4.5 V | 5 | |
| Negative switching threshold | VT- | 1.2 | 3 | V | VCC = 6 V | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.2 | 1 | V | VCC = 2 V; guaranteed by design | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.4 | 1.4 | V | VCC = 4.5 V; guaranteed by design | 5 | |
| Hysteresis (VT+ - VT-) | ΔVT | 0.6 | 1.6 | V | VCC = 6 V; guaranteed by design | 5 | |
| High-level output voltage | VOH | 4 | 4.3 | V | IOH = -6 mA, VCC = 4.5 V | 5 | |
| High-level output voltage | VOH | 5.4 | 5.75 | V | IOH = -7.8 mA, VCC = 6 V | 5 | |
| Low-level output voltage | VOL | 0.18 | 0.3 | V | IOL = 6 mA, VCC = 4.5 V | 5 | |
| Low-level output voltage | VOL | 0.22 | 0.33 | V | IOL = 7.8 mA, VCC = 6 V | 5 | |
| Input leakage current | II | -1000 | 100 | 1000 | nA | VI = VCC or 0, 6 V | 5 |
| Supply current | ICC | 0.1 | 2 | µA | VI = VCC or 0, IO = 0, 6 V | 5 | |
| Clock frequency | fclock | 45 | MHz | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 5 | ||
| Clock frequency | fclock | 140 | MHz | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 5 | ||
| Clock frequency | fclock | 155 | MHz | VCC = 6 V; CL = 50 pF; -40°C to 125°C | 5 | ||
| Pulse duration CLR low | tw | 5 | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 5 | ||
| Pulse duration CLR low | tw | 4 | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 5 | ||
| Setup time SH/LD low before CLK↑ | tsu | 18 | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 | ||
| Setup time SH/LD low before CLK↑ | tsu | 6 | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 | ||
| Setup time SER before CLK↑ | tsu | 14 | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 | ||
| Setup time SER before CLK↑ | tsu | 6 | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 | ||
| Setup time CLK INH low before CLK↑ | tsu | 6 | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 | ||
| Setup time CLK INH low before CLK↑ | tsu | 3 | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 | ||
| Setup time data before CLK↑ | tsu | 14 | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 | ||
| Setup time data before CLK↑ | tsu | 5 | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 | ||
| Setup time CLR inactive before CLK↑ | tsu | 22 | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 | ||
| Setup time CLR inactive before CLK↑ | tsu | 8 | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 | ||
| Propagation delay CLK to QH | tpd | 24 | 40 | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 | |
| Propagation delay CLK to QH | tpd | 9 | 15 | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 | |
| Propagation delay CLK to QH | tpd | 8 | 12 | ns | VCC = 6 V; CL = 50 pF; -40°C to 125°C | 6 | |
| Propagation delay CLR to QH | tPHL | 40 | 60 | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 | |
| Propagation delay CLR to QH | tPHL | 14 | 21 | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 | |
| Propagation delay CLR to QH | tPHL | 11 | 18 | ns | VCC = 6 V; CL = 50 pF; -40°C to 125°C | 6 | |
| Transition time any output | tt | 9 | 17 | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 7 | |
| Transition time any output | tt | 5 | 8 | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 7 | |
| Transition time any output | tt | 4 | 7 | ns | VCC = 6 V; CL = 50 pF; -40°C to 125°C | 7 |
CAD (KiCad official)
- Symbol:
SN74HCS166PWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74hcs166pwr-etched.step/sn74hcs166pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hcs166pwr.step/sn74hcs166pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (27 pp, sha256
30d84a35c1b3be4e, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HCS166PWR
**Texas Instruments** · Shift Registers · TSSOP-16
SN74HCS166PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SER | input | Serial input to the 8-bit shift register. |
| 2 | A | input | Parallel data input A for parallel loading when SH/LD is low. |
| 3 | B | input | Parallel data input B for parallel loading when SH/LD is low. |
| 4 | C | input | Parallel data input C for parallel loading when SH/LD is low. |
| 5 | D | input | Parallel data input D for parallel loading when SH/LD is low. |
| 6 | CLK INH | input | Clock inhibit input that controls whether the clock is enabled. |
| 7 | CLK | input | Clock input, positive edge triggered. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | CLR | input | Clear input, active low. |
| 10 | E | input | Parallel data input E for parallel loading when SH/LD is low. |
| 11 | F | input | Parallel data input F for parallel loading when SH/LD is low. |
| 12 | G | input | Parallel data input G for parallel loading when SH/LD is low. |
| 13 | QH | output | QH serial output of the shift register. |
| 14 | H | input | Parallel data input H for parallel loading when SH/LD is low. |
| 15 | SH/LD | input | Shift/load input: enables shifting when high and loads parallel data when low. |
| 16 | VCC | power_in | Positive supply; recommended supply voltage range is 2 V to 6 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2 | 5 | 6 | V | Recommended operating conditions, free-air temperature range | 4 |
| Input voltage | VI | 0 | | | V | Maximum is VCC | 4 |
| Output voltage | VO | 0 | | | V | Maximum is VCC | 4 |
| Ambient temperature | TA | -40 | | 125 | °C | Operating free-air temperature range | 4 |
| Supply voltage | VCC | -0.5 | | 7 | V | | 4 |
| Input clamp current | IIK | -20 | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| Output clamp current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 |
| Continuous output current | IO | -35 | | 35 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND | | -70 | | 70 | mA | | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Junction-to-ambient thermal resistance (PW TSSOP) | RθJA | | 141.2 | | °C/W | PW (TSSOP) 16 pins | 4 |
| Junction-to-case (top) thermal resistance (PW TSSOP) | RθJC(top) | | 78.8 | | °C/W | PW (TSSOP) 16 pins | 4 |
| Junction-to-board thermal resistance (PW TSSOP) | RθJB | | 85.8 | | °C/W | PW (TSSOP) 16 pins | 4 |
| Positive switching threshold | VT+ | 0.7 | | 1.5 | V | VCC = 2 V | 5 |
| Positive switching threshold | VT+ | 1.7 | | 3.15 | V | VCC = 4.5 V | 5 |
| Positive switching threshold | VT+ | 2.1 | | 4.2 | V | VCC = 6 V | 5 |
| Negative switching threshold | VT- | 0.3 | | 1 | V | VCC = 2 V | 5 |
| Negative switching threshold | VT- | 0.9 | | 2.2 | V | VCC = 4.5 V | 5 |
| Negative switching threshold | VT- | 1.2 | | 3 | V | VCC = 6 V | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.2 | | 1 | V | VCC = 2 V; guaranteed by design | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.4 | | 1.4 | V | VCC = 4.5 V; guaranteed by design | 5 |
| Hysteresis (VT+ - VT-) | ΔVT | 0.6 | | 1.6 | V | VCC = 6 V; guaranteed by design | 5 |
| High-level output voltage | VOH | 4 | 4.3 | | V | IOH = -6 mA, VCC = 4.5 V | 5 |
| High-level output voltage | VOH | 5.4 | 5.75 | | V | IOH = -7.8 mA, VCC = 6 V | 5 |
| Low-level output voltage | VOL | | 0.18 | 0.3 | V | IOL = 6 mA, VCC = 4.5 V | 5 |
| Low-level output voltage | VOL | | 0.22 | 0.33 | V | IOL = 7.8 mA, VCC = 6 V | 5 |
| Input leakage current | II | -1000 | 100 | 1000 | nA | VI = VCC or 0, 6 V | 5 |
| Supply current | ICC | | 0.1 | 2 | µA | VI = VCC or 0, IO = 0, 6 V | 5 |
| Clock frequency | fclock | 45 | | | MHz | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 5 |
| Clock frequency | fclock | 140 | | | MHz | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 5 |
| Clock frequency | fclock | 155 | | | MHz | VCC = 6 V; CL = 50 pF; -40°C to 125°C | 5 |
| Pulse duration CLR low | tw | 5 | | | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 5 |
| Pulse duration CLR low | tw | 4 | | | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 5 |
| Setup time SH/LD low before CLK↑ | tsu | 18 | | | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 |
| Setup time SH/LD low before CLK↑ | tsu | 6 | | | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 |
| Setup time SER before CLK↑ | tsu | 14 | | | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 |
| Setup time SER before CLK↑ | tsu | 6 | | | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 |
| Setup time CLK INH low before CLK↑ | tsu | 6 | | | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 |
| Setup time CLK INH low before CLK↑ | tsu | 3 | | | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 |
| Setup time data before CLK↑ | tsu | 14 | | | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 |
| Setup time data before CLK↑ | tsu | 5 | | | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 |
| Setup time CLR inactive before CLK↑ | tsu | 22 | | | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 |
| Setup time CLR inactive before CLK↑ | tsu | 8 | | | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 |
| Propagation delay CLK to QH | tpd | | 24 | 40 | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 |
| Propagation delay CLK to QH | tpd | | 9 | 15 | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 |
| Propagation delay CLK to QH | tpd | | 8 | 12 | ns | VCC = 6 V; CL = 50 pF; -40°C to 125°C | 6 |
| Propagation delay CLR to QH | tPHL | | 40 | 60 | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 6 |
| Propagation delay CLR to QH | tPHL | | 14 | 21 | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 6 |
| Propagation delay CLR to QH | tPHL | | 11 | 18 | ns | VCC = 6 V; CL = 50 pF; -40°C to 125°C | 6 |
| Transition time any output | tt | | 9 | 17 | ns | VCC = 2 V; CL = 50 pF; -40°C to 125°C | 7 |
| Transition time any output | tt | | 5 | 8 | ns | VCC = 4.5 V; CL = 50 pF; -40°C to 125°C | 7 |
| Transition time any output | tt | | 4 | 7 | ns | VCC = 6 V; CL = 50 pF; -40°C to 125°C | 7 |
## CAD (KiCad official)
- Symbol: `SN74HCS166PWR`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `sn74hcs166pwr-etched.step` / `sn74hcs166pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hcs166pwr.step` / `sn74hcs166pwr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74hcs166.pdf) (27 pp, sha256 `30d84a35c1b3be4e`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hcs166pwr-datasheet.pdf)