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SN74HCS11QDRQ1
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HCS11QDRQ1
Texas Instruments · Logic Gates · SOIC-14
SN74HCS11QDRQ1 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input A of gate 1 of the three independent 3-input AND gates (Y = A·B·C); Schmitt-trigger input, so it has no input transition-rate requirement, and unused inputs must be tied to VCC or GND. |
| 2 | 1B | input | Input B of gate 1 (Y = A·B·C); Schmitt-trigger input, and unused inputs must be tied to VCC or GND rather than left floating. |
| 3 | 2A | input | Input A of gate 2 (Y = A·B·C); Schmitt-trigger input, and unused inputs must be tied to VCC or GND rather than left floating. |
| 4 | 2B | input | Input B of gate 2 (Y = A·B·C); Schmitt-trigger input, and unused inputs must be tied to VCC or GND rather than left floating. |
| 5 | 2C | input | Input C of gate 2 (Y = A·B·C); Schmitt-trigger input, and unused inputs must be tied to VCC or GND rather than left floating. |
| 6 | 2Y | output | Output Y of gate 2, a balanced CMOS push-pull output; the datasheet limits output current to ±35 mA continuous (VO = 0 to VCC). |
| 7 | GND | power_in | Ground reference pin; the continuous current through VCC or GND must not exceed ±50 mA. |
| 8 | 3Y | output | Output Y of gate 3, a balanced CMOS push-pull output; the datasheet limits output current to ±35 mA continuous (VO = 0 to VCC). |
| 9 | 3A | input | Input A of gate 3 (Y = A·B·C); Schmitt-trigger input, and unused inputs must be tied to VCC or GND rather than left floating. |
| 10 | 3B | input | Input B of gate 3 (Y = A·B·C); Schmitt-trigger input, and unused inputs must be tied to VCC or GND rather than left floating. |
| 11 | 3C | input | Input C of gate 3 (Y = A·B·C); Schmitt-trigger input, and unused inputs must be tied to VCC or GND rather than left floating. |
| 12 | 1Y | output | Output Y of gate 1, a balanced CMOS push-pull output; the datasheet limits output current to ±35 mA continuous (VO = 0 to VCC). |
| 13 | 1C | input | Input C of gate 1 (Y = A·B·C); Schmitt-trigger input, and unused inputs must be tied to VCC or GND rather than left floating. |
| 14 | VCC | power_in | Positive supply; the recommended supply range is 2 V to 6 V, with a 6 V absolute maximum of 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 3 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < -0.5 or VI > VCC + 0.5 | 3 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < -0.5 or VO > VCC + 0.5 | 3 | |
| Continuous output current | IO | -35 | 35 | mA | VO = 0 to VCC | 3 | |
| Continuous current through VCC or GND | -50 | 50 | mA | 3 | |||
| Junction temperature | TJ | 150 | °C | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Supply voltage (recommended) | VCC | 2 | 5 | 6 | V | 4 | |
| Input voltage (minimum; maximum printed as VCC) | VI | 0 | V | 4 | |||
| Output voltage (minimum; maximum printed as VCC) | VO | 0 | V | 4 | |||
| Ambient temperature | TA | -55 | 125 | °C | 4 | ||
| Positive switching threshold, VCC = 2 V | VT+ | 0.7 | 1.5 | V | 4 | ||
| Positive switching threshold, VCC = 4.5 V | VT+ | 1.7 | 3.15 | V | 4 | ||
| Positive switching threshold, VCC = 6 V | VT+ | 2.1 | 4.2 | V | 4 | ||
| Negative switching threshold, VCC = 2 V | VT- | 0.3 | 1 | V | 4 | ||
| Negative switching threshold, VCC = 4.5 V | VT- | 0.9 | 2.2 | V | 4 | ||
| Negative switching threshold, VCC = 6 V | VT- | 1.2 | 3 | V | 4 | ||
| Hysteresis, VCC = 2 V | ΔVT | 0.2 | 1 | V | 4 | ||
| Hysteresis, VCC = 4.5 V | ΔVT | 0.4 | 1.4 | V | 4 | ||
| Hysteresis, VCC = 6 V | ΔVT | 0.6 | 1.6 | V | 4 | ||
| Low-level output voltage, VCC = 2 V to 6 V | VOL | 0.002 | 0.1 | V | VI = VIH or VIL; IOL = 20 µA | 4 | |
| High-level output voltage, VCC = 4.5 V | VOH | 4 | 4.3 | V | VI = VIH or VIL; IOH = -6 mA | 4 | |
| High-level output voltage, VCC = 6 V | VOH | 5.4 | 5.75 | V | VI = VIH or VIL; IOH = -7.8 mA | 4 | |
| Low-level output voltage, VCC = 4.5 V | VOL | 0.18 | 0.3 | V | VI = VIH or VIL; IOL = 6 mA | 4 | |
| Low-level output voltage, VCC = 6 V | VOL | 0.22 | 0.33 | V | VI = VIH or VIL; IOL = 7.8 mA | 4 | |
| Input leakage current, VCC = 6 V | II | -1000 | 1000 | nA | VI = VCC or 0 | 4 | |
| Supply current, VCC = 6 V | ICC | 0.1 | 2 | µA | VI = VCC or 0, IO = 0 | 4 | |
| Input capacitance, VCC = 2 V to 6 V | Ci | 1 | 5 | pF | 4 | ||
| Propagation delay A, B or C to Y, VCC = 2 V | tpd | 13 | 40 | ns | 5 | ||
| Propagation delay A, B or C to Y, VCC = 4.5 V | tpd | 6 | 17 | ns | 5 | ||
| Propagation delay A, B or C to Y, VCC = 6 V | tpd | 5 | 16 | ns | 5 | ||
| Transition time Y, VCC = 2 V | tt | 9 | 17 | ns | 5 | ||
| Transition time Y, VCC = 4.5 V | tt | 5 | 8 | ns | 5 | ||
| Transition time Y, VCC = 6 V | tt | 4 | 7 | ns | 5 | ||
| Junction-to-ambient thermal resistance, D (SOIC) 14-pin | RθJA | 133.6 | °C/W | D (SOIC) 14 pins | 4 | ||
| Junction-to-case (top) thermal resistance, D (SOIC) 14-pin | RθJC(top) | 89 | °C/W | D (SOIC) 14 pins | 4 | ||
| Junction-to-board thermal resistance, D (SOIC) 14-pin | RθJB | 89.5 | °C/W | D (SOIC) 14 pins | 4 | ||
| Junction-to-top characterization parameter, D (SOIC) 14-pin | ΨJT | 45.5 | °C/W | D (SOIC) 14 pins | 4 | ||
| Junction-to-board characterization parameter, D (SOIC) 14-pin | ΨJB | 89.1 | °C/W | D (SOIC) 14 pins | 4 |
CAD (KiCad official)
- Symbol:
SN74HCS11QDRQ1 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74hcs11qdrq1-etched.step/sn74hcs11qdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hcs11qdrq1.step/sn74hcs11qdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (22 pp, sha256
cb6e885509036dfe, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).