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SN74HCS10QDRQ1

Texas Instruments · Logic Gates · SOIC-14

SN74HCS10QDRQ1 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1A	input	Channel 1 input A of the three-input NAND gate, a CMOS Schmitt-trigger input.
2	1B	input	Channel 1 input B of the three-input NAND gate, a CMOS Schmitt-trigger input.
3	2A	input	Channel 2 input A of the three-input NAND gate, a CMOS Schmitt-trigger input.
4	2B	input	Channel 2 input B of the three-input NAND gate, a CMOS Schmitt-trigger input.
5	2C	input	Channel 2 input C of the three-input NAND gate, a CMOS Schmitt-trigger input.
6	2Y	output	Channel 2 NAND gate output Y, a balanced CMOS push-pull output.
7	GND	power_in	Ground reference for the device.
8	3Y	output	Channel 3 NAND gate output Y, a balanced CMOS push-pull output.
9	3A	input	Channel 3 input A of the three-input NAND gate, a CMOS Schmitt-trigger input.
10	3B	input	Channel 3 input B of the three-input NAND gate, a CMOS Schmitt-trigger input.
11	3C	input	Channel 3 input C of the three-input NAND gate, a CMOS Schmitt-trigger input.
12	1Y	output	Channel 1 NAND gate output Y, a balanced CMOS push-pull output.
13	1C	input	Channel 1 input C of the three-input NAND gate, a CMOS Schmitt-trigger input.
14	VCC	power_in	Positive supply; the recommended operating supply range is 2 V to 6 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-14
Category	Logic
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	-0.5		7	V		3
Input clamp current	IIK	-20		20	mA	VI < -0.5 V or VI > VCC + 0.5 V	3
Output clamp current	IOK	-20		20	mA	VI < -0.5 V or VI > VCC + 0.5 V	3
Continuous output current	IO	-35		35	mA	VO = 0 to VCC	3
Continuous current through VCC or GND		-70		70	mA		3
Junction temperature	TJ			150	°C		3
Storage temperature	Tstg	-65		150	°C		3
Supply voltage	VCC	2	5	6	V		4
Input voltage	VI	0			V		4
Output voltage	VO	0			V		4
Ambient temperature	TA	-40		125	°C		4
Positive switching threshold	VT+	0.7		1.5	V	VCC = 2 V	4
Positive switching threshold	VT+	1.7		3.15	V	VCC = 4.5 V	4
Positive switching threshold	VT+	2.1		4.2	V	VCC = 6 V	4
Negative switching threshold	VT-	0.3		1	V	VCC = 2 V	4
Negative switching threshold	VT-	0.9		2.2	V	VCC = 4.5 V	4
Negative switching threshold	VT-	1.2		3	V	VCC = 6 V	4
Hysteresis (VT+ - VT-)	ΔVT	0.2		1	V	VCC = 2 V	4
Hysteresis (VT+ - VT-)	ΔVT	0.4		1.4	V	VCC = 4.5 V	4
Hysteresis (VT+ - VT-)	ΔVT	0.6		1.6	V	VCC = 6 V	4
High-level output voltage	VOH	4	4.3		V	VI = VIH or VIL; IOH = -6 mA; VCC = 4.5 V	4
High-level output voltage	VOH	5.4	5.75		V	VI = VIH or VIL; IOH = -7.8 mA; VCC = 6 V	4
Low-level output voltage	VOL		0.002	0.1	V	VI = VIH or VIL; IOL = 20 µA; VCC = 2 V to 6 V	4
Low-level output voltage	VOL		0.18	0.3	V	VI = VIH or VIL; IOL = 6 mA; VCC = 4.5 V	4
Low-level output voltage	VOL		0.22	0.33	V	VI = VIH or VIL; IOL = 7.8 mA; VCC = 6 V	4
Input leakage current	II	-1000	100	1000	nA	VI = VCC or 0; VCC = 6 V	4
Supply current	ICC		0.1	2	µA	VI = VCC or 0, IO = 0; VCC = 6 V	4
Propagation delay A or B or C to Y	tpd		14	40	ns	CL = 50 pF; VCC = 2 V	5
Propagation delay A or B or C to Y	tpd		6	17	ns	CL = 50 pF; VCC = 4.5 V	5
Propagation delay A or B or C to Y	tpd		5	16	ns	CL = 50 pF; VCC = 6 V	5
Transition time Y	tt		9	16	ns	CL = 50 pF; VCC = 2 V	5
Transition time Y	tt		5	9	ns	CL = 50 pF; VCC = 4.5 V	5
Transition time Y	tt		4	8	ns	CL = 50 pF; VCC = 6 V	5
Junction-to-ambient thermal resistance (D, SOIC-14)	RθJA		133.6		°C/W	D (SOIC) 14 pins	4
Junction-to-case (top) thermal resistance (D, SOIC-14)	RθJC(top)		89		°C/W	D (SOIC) 14 pins	4
Junction-to-board thermal resistance (D, SOIC-14)	RθJB		89.5		°C/W	D (SOIC) 14 pins	4
Junction-to-top characterization parameter (D, SOIC-14)	ΨJT		45.5		°C/W	D (SOIC) 14 pins	4
Junction-to-board characterization parameter (D, SOIC-14)	ΨJB		89.1		°C/W	D (SOIC) 14 pins	4

CAD (KiCad official)

Symbol: SN74HCS10QDRQ1
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)
3D model files: sn74hcs10qdrq1-etched.step / sn74hcs10qdrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hcs10qdrq1.step / sn74hcs10qdrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (22 pp, sha256 705cac84369e848a, retrieved 2026-10-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF