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SN74HCS10DR

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Texas Instruments Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icssn74hcs10drfactory-2.0.0extractor-text

Verified SN74HCS10DR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN74HCS10DR · SOIC-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 26-page datasheet
  • ✓distributor: lcsc C2869826, digikey 296-SN74HCS10DRTR-ND, mouser 595-SN74HCS10DR
  • ✓family: SOIC-14_3.9x8.7mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-l5rcxher/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.20)
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn74hcs10dr.kicad_sym✓ sn74hcs10dr.kicad_mod✓ sn74hcs10dr.step
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Contents

README

markdown

SN74HCS10DR

Texas Instruments · Gates · SOIC-14

SN74HCS10DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Channel 1 NAND gate input A with Schmitt-trigger input, operating 0 V to VCC.
2 1B input Channel 1 NAND gate input B with Schmitt-trigger input, operating 0 V to VCC.
3 2A input Channel 2 NAND gate input A with Schmitt-trigger input, operating 0 V to VCC.
4 2B input Channel 2 NAND gate input B with Schmitt-trigger input, operating 0 V to VCC.
5 2C input Channel 2 NAND gate input C with Schmitt-trigger input, operating 0 V to VCC.
6 2Y output Channel 2 NAND gate output Y, with ±7.8 mA drive at 5 V and ±35 mA absolute maximum continuous output current.
7 GND power_in Ground pin; continuous current through VCC or GND is limited to ±70 mA absolute maximum.
8 3Y output Channel 3 NAND gate output Y, with ±7.8 mA drive at 5 V and ±35 mA absolute maximum continuous output current.
9 3A input Channel 3 NAND gate input A with Schmitt-trigger input, operating 0 V to VCC.
10 3B input Channel 3 NAND gate input B with Schmitt-trigger input, operating 0 V to VCC.
11 3C input Channel 3 NAND gate input C with Schmitt-trigger input, operating 0 V to VCC.
12 1Y output Channel 1 NAND gate output Y, with ±7.8 mA drive at 5 V and ±35 mA absolute maximum continuous output current.
13 1C input Channel 1 NAND gate input C with Schmitt-trigger input, operating 0 V to VCC.
14 VCC power_in Positive supply, recommended 2 V to 6 V and absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Positive switching threshold VT+ 1.13 1.26 1.37 V VCC = 2V 5
Positive switching threshold VT+ 2.31 2.47 2.66 V VCC = 4.5V 5
Positive switching threshold VT+ 2.99 3.18 3.44 V VCC = 6V 5
Negative switching threshold VT- 0.55 0.62 0.71 V VCC = 2V 5
Negative switching threshold VT- 1.21 1.36 1.5 V VCC = 4.5V 5
Negative switching threshold VT- 1.56 1.79 1.99 V VCC = 6V 5
Hysteresis VT+ - VT- ΔVT 0.54 0.64 0.71 V VCC = 2V 5
Hysteresis VT+ - VT- ΔVT 0.94 1.11 1.27 V VCC = 4.5V 5
Hysteresis VT+ - VT- ΔVT 1.2 1.38 1.57 V VCC = 6V 5
High-level output voltage VOH 4 4.3 V VI = VIH or VIL, IOH = -6mA, VCC = 4.5V 5
High-level output voltage VOH 5.4 5.75 V VI = VIH or VIL, IOH = -7.8mA, VCC = 6V 5
Low-level output voltage VOL 0.002 0.1 V VI = VIH or VIL, IOL = 20µA, VCC = 2V to 6V 5
Low-level output voltage VOL 0.18 0.3 V VI = VIH or VIL, IOL = 4mA, VCC = 4.5V 5
Low-level output voltage VOL 0.22 0.33 V VI = VIH or VIL, IOL = 7.8mA, VCC = 6V 5
Input leakage current II -1000 100 1000 nA VI = VCC or 0, VCC = 6V 5
Supply current ICC 0.1 2 µA VI = VCC or 0, IO = 0, VCC = 6V 5
Input capacitance Ci 5 pF VCC = 2V to 6V 5
Propagation delay A or B or C to Y tpd 14 40 ns CL = 50pF, VCC = 2V 5
Propagation delay A or B or C to Y tpd 6 17 ns CL = 50pF, VCC = 4.5V 5
Propagation delay A or B or C to Y tpd 5 16 ns CL = 50pF, VCC = 6V 5
Transition time Y tt 9 16 ns CL = 50pF, VCC = 2V 5
Transition time Y tt 5 9 ns CL = 50pF, VCC = 4.5V 5
Transition time Y tt 4 8 ns CL = 50pF, VCC = 6V 5
Supply voltage VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < -0.5V or VI > VCC + 0.5V 4
Output clamp current IOK -20 20 mA VI < -0.5V or VI > VCC + 0.5V 4
Continuous output current IO -35 35 mA VO = 0 to VCC 4
Continuous current through VCC or GND -70 70 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VCC 2 5 6 V 4
Ambient temperature TA -55 125 °C 4
Junction-to-ambient thermal resistance RθJA 133.6 °C/W D (SOIC) 14 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 89 °C/W D (SOIC) 14 pins 4
Junction-to-board thermal resistance RθJB 89.5 °C/W D (SOIC) 14 pins 4
Junction-to-top characterization parameter ΨJT 45.5 °C/W D (SOIC) 14 pins 4
Junction-to-board characterization parameter ΨJB 89.1 °C/W D (SOIC) 14 pins 4

CAD (KiCad official)

  • Symbol: SN74HCS10DR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74hcs10dr-etched.step / sn74hcs10dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hcs10dr.step / sn74hcs10dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 9ab247881b8b2518, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF