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Ray Publish 0.1.0 b5ee780 5d ago

SN74HC86DTR

XBLW · Logic Gates · SOP-14

SN74HC86DTR from XBLW, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 data input A.
2 1B input Gate 1 data input B.
3 1Y output Gate 1 data output.
4 2A input Gate 2 data input A.
5 2B input Gate 2 data input B.
6 2Y output Gate 2 data output.
7 GND power_in Ground (0 V).
8 3Y output Gate 3 data output.
9 3A input Gate 3 data input A.
10 3B input Gate 3 data input B.
11 4Y output Gate 4 data output.
12 4A input Gate 4 data input A.
13 4B input Gate 4 data input B.
14 VCC power_in Supply voltage; recommended 2.0 V to 6.0 V, absolute maximum +7 V.

Key specifications

Parameter Value
Manufacturer XBLW
Package SOP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74HC86DTR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74hc86dtr-etched.step / sn74hc86dtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc86dtr.step / sn74hc86dtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XBLW datasheet (16 pp, sha256 f38c0566b404464a, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF