component
SN74HC74QPWRG4Q1
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SN74HC74QPWRG4Q1
Texas Instruments · Flip Flops · TSSOP-14
SN74HC74QPWRG4Q1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Channel 1 clear input, active low; driving it low forces Q low and Q̄ high while PRE is high. |
| 2 | 1D | input | Channel 1 data input, which is transferred to Q on the positive edge of 1CLK when PRE and CLR are inactive. |
| 3 | 1CLK | input | Channel 1 positive-edge-triggered clock input. |
| 4 | 1PRE | input | Channel 1 preset input, active low; driving it low forces Q high and Q̄ low while CLR is high. |
| 5 | 1Q | output | Channel 1 true output. |
| 6 | 1Q̄ | output | Channel 1 inverted output. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 2Q̄ | output | Channel 2 inverted output. |
| 9 | 2Q | output | Channel 2 true output. |
| 10 | 2PRE | input | Channel 2 preset input, active low; driving it low forces Q high and Q̄ low while CLR is high. |
| 11 | 2CLK | input | Channel 2 positive-edge-triggered clock input. |
| 12 | 2D | input | Channel 2 data input, which is transferred to Q on the positive edge of 2CLK when PRE and CLR are inactive. |
| 13 | 2CLR | input | Channel 2 clear input, active low; driving it low forces Q low and Q̄ high while PRE is high. |
| 14 | VCC | power_in | Positive supply; recommended operating range is 2 V to 6 V, with an absolute maximum of 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74HC74QPWRG4Q1 - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74hc74qpwrg4q1-etched.step/sn74hc74qpwrg4q1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc74qpwrg4q1.step/sn74hc74qpwrg4q1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (25 pp, sha256
cc65f48c07b236ea, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HC74QPWRG4Q1
**Texas Instruments** · Flip Flops · TSSOP-14
SN74HC74QPWRG4Q1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Channel 1 clear input, active low; driving it low forces Q low and Q̄ high while PRE is high. |
| 2 | 1D | input | Channel 1 data input, which is transferred to Q on the positive edge of 1CLK when PRE and CLR are inactive. |
| 3 | 1CLK | input | Channel 1 positive-edge-triggered clock input. |
| 4 | 1PRE | input | Channel 1 preset input, active low; driving it low forces Q high and Q̄ low while CLR is high. |
| 5 | 1Q | output | Channel 1 true output. |
| 6 | 1Q̄ | output | Channel 1 inverted output. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 2Q̄ | output | Channel 2 inverted output. |
| 9 | 2Q | output | Channel 2 true output. |
| 10 | 2PRE | input | Channel 2 preset input, active low; driving it low forces Q high and Q̄ low while CLR is high. |
| 11 | 2CLK | input | Channel 2 positive-edge-triggered clock input. |
| 12 | 2D | input | Channel 2 data input, which is transferred to Q on the positive edge of 2CLK when PRE and CLR are inactive. |
| 13 | 2CLR | input | Channel 2 clear input, active low; driving it low forces Q low and Q̄ high while PRE is high. |
| 14 | VCC | power_in | Positive supply; recommended operating range is 2 V to 6 V, with an absolute maximum of 7 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## CAD (KiCad official)
- Symbol: `SN74HC74QPWRG4Q1`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74hc74qpwrg4q1-etched.step` / `sn74hc74qpwrg4q1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc74qpwrg4q1.step` / `sn74hc74qpwrg4q1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hc74-q1) (25 pp, sha256 `cc65f48c07b236ea`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hc74qpwrg4q1-datasheet.pdf)