SN74HC74

{
  "schema_version": 1,
  "type": "component",
  "slug": "sn74hc74",
  "title": "SN74HC74",
  "brief": "TI dual D-type positive-edge flip-flop, SOIC-14. Async preset/clear, HC CMOS, 2-6 V. Datasheet-verified.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "flip-flop",
    "d-flip-flop",
    "74hc",
    "soic-14",
    "texas-instruments"
  ],
  "component": {
    "mpn": "SN74HC74",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic IC",
    "subcategory": "Dual D flip-flop",
    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hc74.pdf",
    "parts": {
      "symbol": "sn74hc74.kicad_sym",
      "footprint": "sn74hc74.kicad_mod",
      "model_3d": "sn74hc74-etched.glb",
      "model_3d_plain": "sn74hc74.glb",
      "lbr": "sn74hc74.lbr",
      "model_3d_step": "sn74hc74-etched.step",
      "model_3d_step_plain": "sn74hc74.step"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "1CLR",
        "type": "input",
        "description": "Channel 1 asynchronous clear input, active low. Driving low forces 1Q low and 1Q̄ high regardless of CLK/D. VIL ≤ 1.35 V @ VCC=4.5 V; input clamp current ±20 mA max."
      },
      {
        "number": "2",
        "name": "1D",
        "type": "input",
        "description": "Channel 1 data input; sampled on the rising edge of 1CLK. Setup time 20 ns typ @ VCC=4.5 V, hold time 0 ns."
      },
      {
        "number": "3",
        "name": "1CLK",
        "type": "input",
        "description": "Channel 1 positive-edge-triggered clock input. Maximum clock frequency 31 MHz @ VCC=4.5 V, 36 MHz @ VCC=6 V."
      },
      {
        "number": "4",
        "name": "1PRE",
        "type": "input",
        "description": "Channel 1 asynchronous preset input, active low. Driving low forces 1Q high and 1Q̄ low regardless of CLK/D. Minimum pulse width 20 ns @ VCC=4.5 V."
      },
      {
        "number": "5",
        "name": "1Q",
        "type": "output",
        "description": "Channel 1 flip-flop output. Follows 1D at the rising edge of 1CLK. VOH ≥ 3.98 V @ IOH=-4 mA, VCC=4.5 V; propagation delay 20 ns typ from CLK."
      },
      {
        "number": "6",
        "name": "1Q̄",
        "type": "output",
        "description": "Channel 1 inverted flip-flop output, complement of 1Q."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Device ground reference (0 V)."
      },
      {
        "number": "8",
        "name": "2Q̄",
        "type": "output",
        "description": "Channel 2 inverted flip-flop output, complement of 2Q."
      },
      {
        "number": "9",
        "name": "2Q",
        "type": "output",
        "description": "Channel 2 flip-flop output. Follows 2D at the rising edge of 2CLK."
      },
      {
        "number": "10",
        "name": "2PRE",
        "type": "input",
        "description": "Channel 2 asynchronous preset input, active low. Driving low forces 2Q high and 2Q̄ low regardless of CLK/D."
      },
      {
        "number": "11",
        "name": "2CLK",
        "type": "input",
        "description": "Channel 2 positive-edge-triggered clock input."
      },
      {
        "number": "12",
        "name": "2D",
        "type": "input",
        "description": "Channel 2 data input; sampled on the rising edge of 2CLK."
      },
      {
        "number": "13",
        "name": "2CLR",
        "type": "input",
        "description": "Channel 2 asynchronous clear input, active low. Driving low forces 2Q low and 2Q̄ high regardless of CLK/D."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply. Operating range 2 V to 6 V (nom 5 V); absolute max 7 V. ICC ≤ 40 µA over temperature."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/sn74hc74.pdf",
        "pages": 41,
        "sha256": "a60d59528e97fe91",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "74HC74",
      "logic_family": "74HC",
      "function_code": "74",
      "function_class": "Flip-Flop",
      "function_name": "Dual D Flip-Flop with Set/Reset",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "sn74hc74.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74hc74-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "c8750e3e746ae3ed9b24f551866852e1e10e7071ece5cab9692576a1d8b4ba0a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Type": "Dual D-type flip-flop",
      "Trigger": "Positive (rising) clock edge",
      "Async controls": "PRE + CLR (active-low)",
      "Outputs": "Q + Q (complementary)",
      "Logic family": "HC (high-speed CMOS)",
      "Supply voltage": "2-6 V",
      "Package": "SOIC-14",
      "Body (L×W×H)": "8.65 × 3.9 × 1.75 mm"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "sn74hc74",
    "74hc74",
    "dual d flip-flop",
    "d-type flip flop"
  ],
  "discovery_pitch": "SN74HC74 dual D-type positive-edge-triggered flip-flop (SOIC-14) with datasheet-verified pinout, KiCad symbol/footprint/3D, and full provenance.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "sn74hc74.kicad_sym",
    "sn74hc74.kicad_mod",
    "sn74hc74.glb",
    "sn74hc74.lbr",
    "docs/hero.png",
    "docs/sn74hc74-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "sn74hc74-etched.step"
  ],
  "variants": [
    {
      "mpn": "SN74HC74D (SOIC-14, tube)",
      "kind": "packaging"
    },
    {
      "mpn": "SN74HC74DR (SOIC-14, tape & reel)",
      "kind": "packaging"
    }
  ]
}