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SN74HC688N

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Texas Instruments Digital Comparators, PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74HC688N

Texas Instruments · Digital Comparators · PDIP-20

SN74HC688N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output enable input; a high level forces the P=Q output high.
2 P0 input Word P data input bit 0, compared against Q0; unused inputs must be held at VCC or GND.
3 Q0 input Word Q data input bit 0, compared against P0; unused inputs must be held at VCC or GND.
4 P1 input Word P data input bit 1, compared against Q1; unused inputs must be held at VCC or GND.
5 Q1 input Word Q data input bit 1, compared against P1; unused inputs must be held at VCC or GND.
6 P2 input Word P data input bit 2, compared against Q2; unused inputs must be held at VCC or GND.
7 Q2 input Word Q data input bit 2, compared against P2; unused inputs must be held at VCC or GND.
8 P3 input Word P data input bit 3, compared against Q3; unused inputs must be held at VCC or GND.
9 Q3 input Word Q data input bit 3, compared against P3; unused inputs must be held at VCC or GND.
10 GND power_in Ground reference pin.
11 P4 input Word P data input bit 4, compared against Q4; unused inputs must be held at VCC or GND.
12 Q4 input Word Q data input bit 4, compared against P4; unused inputs must be held at VCC or GND.
13 P5 input Word P data input bit 5, compared against Q5; unused inputs must be held at VCC or GND.
14 Q5 input Word Q data input bit 5, compared against P5; unused inputs must be held at VCC or GND.
15 P6 input Word P data input bit 6, compared against Q6; unused inputs must be held at VCC or GND.
16 Q6 input Word Q data input bit 6, compared against P6; unused inputs must be held at VCC or GND.
17 P7 input Word P data input bit 7, compared against Q7; unused inputs must be held at VCC or GND.
18 Q7 input Word Q data input bit 7, compared against P7; unused inputs must be held at VCC or GND.
19 P=Q output Active-low identity comparator output; low when P equals Q and OE is low, otherwise high, with ±4 mA drive at 5 V.
20 VCC power_in Supply voltage pin, 2 V to 6 V recommended; a 0.1-µF bypass capacitor is recommended.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Junction temperature TJ 150 ℃ 4
Storage temperature range Tstg -65 150 ℃ 4
Supply voltage VCC 2 5 6 V 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
High-level input voltage VIH 3.15 V VCC = 4.5 V 4
High-level input voltage VIH 4.2 V VCC = 6 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Low-level input voltage VIL 1.35 V VCC = 4.5 V 4
Low-level input voltage VIL 1.8 V VCC = 6 V 4
Input voltage VI 0 6 V max = VCC 4
Output voltage VO 0 6 V max = VCC 4
Input transition time tt 1000 ns VCC = 2 V 4
Input transition time tt 500 ns VCC = 4.5 V 4
Input transition time tt 400 ns VCC = 6 V 4
Operating free-air temperature TA -40 85 °C 4
Junction-to-ambient thermal resistance RθJA 84.6 °C/W N (PDIP) 20 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 72.5 °C/W N (PDIP) 20 pins 4
Junction-to-board thermal resistance RθJB 65.3 °C/W N (PDIP) 20 pins 4
Junction-to-top characterization parameter ψJT 55.3 °C/W N (PDIP) 20 pins 4
Junction-to-board characterization parameter ψJB 65.2 °C/W N (PDIP) 20 pins 4
High-level output voltage VOH 1.9 V VI = VIH or VIL, IOH = -20 μA, VCC = 2 V 5
High-level output voltage VOH 4.4 V VI = VIH or VIL, IOH = -20 μA, VCC = 4.5 V 5
High-level output voltage VOH 5.9 V VI = VIH or VIL, IOH = -20 μA, VCC = 6 V 5
High-level output voltage VOH 3.84 V VI = VIH or VIL, IOH = -4 mA, VCC = 4.5 V 5
High-level output voltage VOH 5.34 V VI = VIH or VIL, IOH = -5.2 mA, VCC = 6 V 5
Low-level output voltage VOL 0.1 V VI = VIH or VIL, IOL = 20 μA, VCC = 2 V 5
Low-level output voltage VOL 0.33 V VI = VIH or VIL, IOL = 4 mA, VCC = 4.5 V 5
Input current II -1000 1000 nA VI = VCC or 0, VCC = 6 V 5
Supply current ICC 80 μA VI = VCC or 0, IO = 0, VCC = 6 V 5
Input capacitance Ci 3 10 pF VCC = 2 V to 6 V 5
Propagation delay P or Q to P=Q tpd 265 ns CL = 50 pF, VCC = 2 V 5
Propagation delay P or Q to P=Q tpd 53 ns CL = 50 pF, VCC = 4.5 V 5
Propagation delay P or Q to P=Q tpd 45 ns CL = 50 pF, VCC = 6 V 5
Propagation delay OE to P=Q tpd 151 ns CL = 50 pF, VCC = 2 V 5
Propagation delay OE to P=Q tpd 30 ns CL = 50 pF, VCC = 4.5 V 5
Propagation delay OE to P=Q tpd 26 ns CL = 50 pF, VCC = 6 V 5
Output transition time tt 95 ns CL = 50 pF, VCC = 2 V 5
Output transition time tt 19 ns CL = 50 pF, VCC = 4.5 V 5
Output transition time tt 16 ns CL = 50 pF, VCC = 6 V 5
Power dissipation capacitance Cpd 40 pF No load, TA = 25℃ 5

CAD (KiCad official)

  • Symbol: SN74HC688N
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: PDIP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74hc688n-etched.step / sn74hc688n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc688n.step / sn74hc688n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 3caff02f31ddd84e, retrieved 2026-10-30, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF