component
SN74HC652DWR
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, SOIC-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 11d ago |
| viewers | 11d ago |
| package.json | 11d ago |
| page.json | 11d ago |
| README.md | 11d ago |
| sn74hc652dwr-etched.glb | 11d ago |
| sn74hc652dwr-etched.step | 11d ago |
| sn74hc652dwr-hero.glb | 11d ago |
| sn74hc652dwr-hero.overlay.json | 11d ago |
| sn74hc652dwr.glb | 11d ago |
| sn74hc652dwr.kicad_mod | 11d ago |
| sn74hc652dwr.kicad_sym | 11d ago |
| sn74hc652dwr.lbr | 11d ago |
| sn74hc652dwr.step | 11d ago |
SN74HC652DWR
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-24
SN74HC652DWR from Texas Instruments, in a SOIC-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLKAB | input | Clock input for the A-bus internal D-type flip-flops; data on the A or B bus is stored on each low-to-high transition of this clock, regardless of the select or output-control terminals. |
| 2 | SAB | input | A-bus select control: a low level selects real-time data transfer and a high level selects stored data. |
| 3 | OEAB | input | Output enable for the A-bus outputs; it should be tied to GND through a pulldown resistor to ensure the high-impedance state during power up or power down. |
| 4 | A1 | bidirectional | A-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 5 | A2 | bidirectional | A-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 6 | A3 | bidirectional | A-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 7 | A4 | bidirectional | A-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 8 | A5 | bidirectional | A-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 9 | A6 | bidirectional | A-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 10 | A7 | bidirectional | A-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 11 | A8 | bidirectional | A-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 12 | GND | power_in | Device ground; all unused inputs must be held at VCC or GND to ensure proper device operation. |
| 13 | B8 | bidirectional | B-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 14 | B7 | bidirectional | B-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 15 | B6 | bidirectional | B-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 16 | B5 | bidirectional | B-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 17 | B4 | bidirectional | B-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 18 | B3 | bidirectional | B-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 19 | B2 | bidirectional | B-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 20 | B1 | bidirectional | B-bus data input/output, 3-state output capable of driving up to 15 LSTTL loads. |
| 21 | OEBA | input | Output enable for the B-bus outputs; it should be tied to VCC through a pullup resistor to ensure the high-impedance state during power up or power down. |
| 22 | SBA | input | B-bus select control: a low level selects real-time data transfer and a high level selects stored data. |
| 23 | CLKBA | input | Clock input for the B-bus internal D-type flip-flops; data on the A or B bus is stored on each low-to-high transition of this clock, regardless of the select or output-control terminals. |
| 24 | VCC | power_in | Supply voltage, recommended operating range 2 V to 6 V; absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-24 |
| Category | Logic |
| Pins | 24 |
CAD (KiCad official)
- Symbol:
SN74HC652DWR - Footprint:
Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm - 3D model: SOIC-24 (KiCad packages3D, STEP)
- 3D model files:
sn74hc652dwr-etched.step/sn74hc652dwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc652dwr.step/sn74hc652dwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (13 pp, sha256
843f10182676a305, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).