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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	7d ago
viewers	sn74hc597n: viewers · Ray	7d ago
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page.json	Set visibility: public · Ray	7d ago
README.md	Publish 0.1.0 · Ray	7d ago
sn74hc597n-etched.glb	Publish 0.1.0 · Ray	7d ago
sn74hc597n-etched.step	sn74hc597n: factory component page (tier=lcsc) · Ray	7d ago
sn74hc597n-hero.glb	sn74hc597n: hero GLB from the etched model (keeps the MPN mark) · Ray	7d ago
sn74hc597n-hero.overlay.json	Publish 0.1.0 · Ray	7d ago
sn74hc597n.glb	Publish 0.1.0 · Ray	7d ago
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sn74hc597n.lbr	Publish 0.1.0 · Ray	7d ago
sn74hc597n.step	Publish 0.1.0 · Ray	7d ago

SN74HC597N

XBLW · Shift Registers · DIP-16

SN74HC597N from XBLW, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	D1	input	Parallel data pin 1; the pin table calls it a parallel data output, but the block diagram shows it as an input to the input flip-flop stage.
2	D2	input	Parallel data pin 2; the pin table calls it a parallel data output, but the block diagram shows it as an input.
3	D3	input	Parallel data pin 3; the pin table calls it a parallel data output, but the block diagram shows it as an input.
4	D4	input	Parallel data pin 4; the pin table calls it a parallel data output, but the block diagram shows it as an input.
5	D5	input	Parallel data pin 5; the pin table calls it a parallel data output, but the block diagram shows it as an input.
6	D6	input	Parallel data pin 6; the pin table calls it a parallel data output, but the block diagram shows it as an input.
7	D7	input	Parallel data pin 7; the pin table calls it a parallel data output, but the block diagram shows it as an input.
8	GND	power_in	Ground (0V).
9	Q	output	Serial data output.
10	MR	input	Asynchronous master reset input, active LOW.
11	SHCP	input	Shift register clock input, LOW-to-HIGH edge-triggered.
12	STCP	input	Storage register clock input, LOW-to-HIGH edge-triggered.
13	PL	input	Parallel load input, active LOW.
14	DS	input	Serial data input.
15	D0	input	Parallel data input 0.
16	VCC	power_in	Supply voltage; recommended 2.0 V to 6.0 V (typ. 5.0 V), absolute maximum -0.5 V to +7 V.

Key specifications

Parameter	Value
Manufacturer	XBLW
Package	DIP-16
Category	Logic
Pins	16

CAD (KiCad official)

Symbol: SN74HC597N
Footprint: Package_DIP:DIP-16_W7.62mm
3D model: DIP-16 (KiCad packages3D, STEP)
3D model files: sn74hc597n-etched.step / sn74hc597n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc597n.step / sn74hc597n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: XBLW datasheet (17 pp, sha256 4c3e3ccc6a562c5d, retrieved 2026-10-15, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF