main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 13d ago
viewers sn74hc595dtr: viewers · Ray 13d ago
package.json Publish 0.1.0 · Ray 13d ago
page.json Set visibility: public · Ray 13d ago
README.md Publish 0.1.0 · Ray 13d ago
sn74hc595dtr-etched.glb sn74hc595dtr: factory component page (tier=lcsc) · Ray 13d ago
sn74hc595dtr-etched.step sn74hc595dtr: factory component page (tier=lcsc) · Ray 13d ago
sn74hc595dtr-hero.glb sn74hc595dtr: hero GLB from the etched model (keeps the MPN mark) · Ray 13d ago
sn74hc595dtr-hero.overlay.json Publish 0.1.0 · Ray 13d ago
sn74hc595dtr.glb Publish 0.1.0 · Ray 13d ago
sn74hc595dtr.kicad_mod Publish 0.1.0 · Ray 13d ago
sn74hc595dtr.kicad_sym Publish 0.1.0 · Ray 13d ago
sn74hc595dtr.lbr Publish 0.1.0 · Ray 13d ago
sn74hc595dtr.step Publish 0.1.0 · Ray 13d ago

SN74HC595DTR

XBLW · Shift Registers · SOP-16

SN74HC595DTR from XBLW, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 output Parallel data output 1 (3-state, high-impedance when OE is HIGH).
2 Q2 output Parallel data output 2 (3-state, high-impedance when OE is HIGH).
3 Q3 output Parallel data output 3 (3-state, high-impedance when OE is HIGH).
4 Q4 output Parallel data output 4 (3-state, high-impedance when OE is HIGH).
5 Q5 output Parallel data output 5 (3-state, high-impedance when OE is HIGH).
6 Q6 output Parallel data output 6 (3-state, high-impedance when OE is HIGH).
7 Q7 output Parallel data output 7 (3-state, high-impedance when OE is HIGH).
8 GND power_in Ground (0 V).
9 Q7S output Serial data output used for cascading to the next device.
10 MR input Master reset, active LOW; a LOW asynchronously resets the shift register.
11 SHCP input Shift register clock input; data shifts on LOW-to-HIGH transitions.
12 STCP input Storage register clock input; shift register data transfers to storage on LOW-to-HIGH transition.
13 OE input Output enable input, active LOW; HIGH puts outputs in high-impedance OFF-state without affecting registers.
14 DS input Serial data input.
15 Q0 output Parallel data output 0 (3-state, high-impedance when OE is HIGH).
16 VCC power_in Supply voltage.

Key specifications

Parameter Value
Manufacturer XBLW
Package SOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74HC595DTR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hc595dtr-etched.step / sn74hc595dtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc595dtr.step / sn74hc595dtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XBLW datasheet (19 pp, sha256 5502d4077590a4a6, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF