# SN74HC595D

**lingxingic** · Shift Registers · SOP-16

SN74HC595D from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1 | tri_state | Parallel 3-state data output Q1 from the 8-bit storage register, with an absolute output current limit of ±35 mA. |
| 2 | Q2 | tri_state | Parallel 3-state data output Q2 from the 8-bit storage register, with an absolute output current limit of ±35 mA. |
| 3 | Q3 | tri_state | Parallel 3-state data output Q3 from the 8-bit storage register, with an absolute output current limit of ±35 mA. |
| 4 | Q4 | tri_state | Parallel 3-state data output Q4 from the 8-bit storage register, with an absolute output current limit of ±35 mA. |
| 5 | Q5 | tri_state | Parallel 3-state data output Q5 from the 8-bit storage register, with an absolute output current limit of ±35 mA. |
| 6 | Q6 | tri_state | Parallel 3-state data output Q6 from the 8-bit storage register, with an absolute output current limit of ±35 mA. |
| 7 | Q7 | tri_state | Parallel 3-state data output Q7 from the 8-bit storage register, with an absolute output current limit of ±35 mA. |
| 8 | GND | power_in | Ground reference, 0 V. |
| 9 | Q7S | output | Serial data output from shift register stage 7, used for cascading devices, with an absolute output current limit of ±25 mA. |
| 10 | MR | input | Asynchronous master reset, active low; a low level resets only the shift register and does not affect the storage register. |
| 11 | SHCP | input | Shift register clock input; data on DS is shifted into the shift register on the rising edge of SHCP. |
| 12 | STCP | input | Storage register clock input; the shift register contents are transferred to the storage register on the rising edge of STCP. |
| 13 | OE | input | Output enable, active low; when high, Qn outputs go to high-impedance, and changes on OE do not affect the register contents. |
| 14 | DS | input | Serial data input to shift register stage 0; a logic high is shifted in on the rising edge of SHCP. |
| 15 | Q0 | tri_state | Parallel 3-state data output Q0 from the 8-bit storage register, with an absolute output current limit of ±35 mA. |
| 16 | VCC | power_in | Supply voltage; absolute maximum 7.0 V, recommended 2.0 V to 6.0 V for SN74HC595 and 4.5 V to 5.5 V for SN74HCT595. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `SN74HC595D`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `sn74hc595d-etched.step` / `sn74hc595d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc595d.step` / `sn74hc595d.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590923056523669504) (23 pp, sha256 `071208edc31feb2f`, retrieved 2026-10-09, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74hc595d-datasheet.pdf)