component
SN74HC590ADWR
Public Made by Adomby adom
Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"component": {
"mpn": "SN74HC590ADWR",
"manufacturer": "Texas Instruments",
"package": "SOIC-16",
"pin_count": 16,
"category": "Logic",
"subcategory": "Counters, Dividers",
"datasheet": "https://www.ti.com/cn/lit/gpn/sn74hc590a",
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"distributor_links": {
"lcsc": "C2675451",
"digikey": "296-14856-2-ND",
"mouser": "595-SN74HC590ADWR"
},
"distributor_check": {
"checked_at": "2026-10-08T20:05:52Z",
"source": "Component Ocean /api/assign-pns",
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"status": "found",
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"pins": [
{
"number": "1",
"name": "QB",
"type": "tri_state",
"description": "Parallel 3-state register output QB of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads."
},
{
"number": "2",
"name": "QC",
"type": "tri_state",
"description": "Parallel 3-state register output QC of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads."
},
{
"number": "3",
"name": "QD",
"type": "tri_state",
"description": "Parallel 3-state register output QD of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads."
},
{
"number": "4",
"name": "QE",
"type": "tri_state",
"description": "Parallel 3-state register output QE of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads."
},
{
"number": "5",
"name": "QF",
"type": "tri_state",
"description": "Parallel 3-state register output QF of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads."
},
{
"number": "6",
"name": "QG",
"type": "tri_state",
"description": "Parallel 3-state register output QG of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads."
},
{
"number": "7",
"name": "QH",
"type": "tri_state",
"description": "Parallel 3-state register output QH of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads."
},
{
"number": "8",
"name": "GND",
"type": "power_in",
"description": "Ground reference for the device."
},
{
"number": "9",
"name": "RCO",
"type": "output",
"description": "Ripple-carry output for cascading; it is connected to CCKEN of a second stage for two-stage expansion or to CCLK of the following stage for longer chains, and is driven by CCLK rising edges (tpd CCLK↑ to RCO)."
},
{
"number": "10",
"name": "CCLR",
"type": "input",
"description": "Direct (asynchronous) clear input for the binary counter; a low level clears the counter independently of CCLK, and the datasheet specifies a minimum CCLR low pulse width."
},
{
"number": "11",
"name": "CCLK",
"type": "input",
"description": "Counter clock input, positive-edge triggered; if tied to RCLK the register is one count behind the counter."
},
{
"number": "12",
"name": "CCKEN",
"type": "input",
"description": "Counter clock enable; a high level inhibits the counter clock (CCKEN must be low before CCLK rises, with listed setup and hold times)."
},
{
"number": "13",
"name": "RCLK",
"type": "input",
"description": "Storage register clock input, positive-edge triggered, which transfers the counter state to the 8-bit output register; it must be set up before the register clock edge relative to CCLK, with the listed timing limits."
},
{
"number": "14",
"name": "OE",
"type": "input",
"description": "Output enable for QA-QH; the switching characteristics show outputs enabled on OE going low and placed in 3-state on OE going high."
},
{
"number": "15",
"name": "QA",
"type": "tri_state",
"description": "Parallel 3-state register output QA of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage, specified from 2 V to 6 V with absolute maximum of 7 V."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
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"factory": "2.0.0",
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"primary_model": "claude-haiku-5-5",
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"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pinout taken from the top-view pin diagram on page 1 and cross-checked against the logic diagram on ; The datasheet does not explicitly state the polarity of OE; the active-low enable and high-level 3-s; Pin descriptions for RCLK, CCLK, CCKEN and CCLR are summarised from the timing and function text; no"
],
"pages_sent": 26,
"cost_usd": 0.0933,
"at": "2026-10-08T20:05:35"
},
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"url": "https://www.ti.com/cn/lit/gpn/sn74hc590a",
"pages": 26,
"sha256": "15f4b455093631e3",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
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"refuses_to_fabricate": true
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