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Contents

README

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SN74HC573NSR

lingxingic · Latches · SOIC-20-208mil

SN74HC573NSR from lingxingic, in a SOIC-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Three-state output enable input, active low; high level disables outputs to high-impedance state
2 D0 input Data input bit 0; latched on LE falling edge when setup and hold times are met
3 D1 input Data input bit 1; latched on LE falling edge when setup and hold times are met
4 D2 input Data input bit 2; latched on LE falling edge when setup and hold times are met
5 D3 input Data input bit 3; latched on LE falling edge when setup and hold times are met
6 D4 input Data input bit 4; latched on LE falling edge when setup and hold times are met
7 D5 input Data input bit 5; latched on LE falling edge when setup and hold times are met
8 D6 input Data input bit 6; latched on LE falling edge when setup and hold times are met
9 D7 input Data input bit 7; latched on LE falling edge when setup and hold times are met
10 GND power_in Ground reference (0V)
11 LE input Latch enable input, active high; when high latches are transparent (Qn=Dn), when low data is stored
12 Q7 tri_state Three-state output bit 7; reflects latched D7 when OE is low, high-impedance when OE is high
13 Q6 tri_state Three-state output bit 6; reflects latched D6 when OE is low, high-impedance when OE is high
14 Q5 tri_state Three-state output bit 5; reflects latched D5 when OE is low, high-impedance when OE is high
15 Q4 tri_state Three-state output bit 4; reflects latched D4 when OE is low, high-impedance when OE is high
16 Q3 tri_state Three-state output bit 3; reflects latched D3 when OE is low, high-impedance when OE is high
17 Q2 tri_state Three-state output bit 2; reflects latched D2 when OE is low, high-impedance when OE is high
18 Q1 tri_state Three-state output bit 1; reflects latched D1 when OE is low, high-impedance when OE is high
19 Q0 tri_state Three-state output bit 0; reflects latched D0 when OE is low, high-impedance when OE is high
20 VCC power_in Power supply voltage; recommended range 2.0V to 6.0V for HC variant, 4.5V to 5.5V for HCT variant

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOIC-20-208mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74HC573NSR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74hc573nsr-etched.step / sn74hc573nsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc573nsr.step / sn74hc573nsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (21 pp, sha256 1e9be54d60bf08ab, retrieved 2026-09-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF