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SN74HC563DWR
Public Made by Adomby adom
Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC563DWR
Texas Instruments · Latches · SOIC-20-300mil
SN74HC563DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low output enable; high places all eight outputs in high-impedance state, and should be tied to VCC through a pullup for high-Z during power up/down. |
| 2 | 1D | input | Data input for latch 1; unused inputs must be held at VCC or GND. |
| 3 | 2D | input | Data input for latch 2; unused inputs must be held at VCC or GND. |
| 4 | 3D | input | Data input for latch 3; unused inputs must be held at VCC or GND. |
| 5 | 4D | input | Data input for latch 4; unused inputs must be held at VCC or GND. |
| 6 | 5D | input | Data input for latch 5; unused inputs must be held at VCC or GND. |
| 7 | 6D | input | Data input for latch 6; unused inputs must be held at VCC or GND. |
| 8 | 7D | input | Data input for latch 7; unused inputs must be held at VCC or GND. |
| 9 | 8D | input | Data input for latch 8; unused inputs must be held at VCC or GND. |
| 10 | GND | power_in | Ground pin. |
| 11 | LE | input | Latch enable; outputs follow the complement of D while high and are latched when low. |
| 12 | 8Q | tri_state | Inverted 3-state output of latch 8, drives up to 15 LSTTL loads with ±6 mA drive at 5 V. |
| 13 | 7Q | tri_state | Inverted 3-state output of latch 7, drives up to 15 LSTTL loads with ±6 mA drive at 5 V. |
| 14 | 6Q | tri_state | Inverted 3-state output of latch 6, drives up to 15 LSTTL loads with ±6 mA drive at 5 V. |
| 15 | 5Q | tri_state | Inverted 3-state output of latch 5, drives up to 15 LSTTL loads with ±6 mA drive at 5 V. |
| 16 | 4Q | tri_state | Inverted 3-state output of latch 4, drives up to 15 LSTTL loads with ±6 mA drive at 5 V. |
| 17 | 3Q | tri_state | Inverted 3-state output of latch 3, drives up to 15 LSTTL loads with ±6 mA drive at 5 V. |
| 18 | 2Q | tri_state | Inverted 3-state output of latch 2, drives up to 15 LSTTL loads with ±6 mA drive at 5 V. |
| 19 | 1Q | tri_state | Inverted 3-state output of latch 1, drives up to 15 LSTTL loads with ±6 mA drive at 5 V. |
| 20 | VCC | power_in | Supply voltage, 2 V to 6 V recommended; bypass with a 0.1-µF capacitor close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74HC563DWR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
sn74hc563dwr-etched.step/sn74hc563dwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc563dwr.step/sn74hc563dwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (19 pp, sha256
6bf51e0a8cdc6fc3, retrieved 2026-10-05, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).